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ds07-13713-3e fujitsu semiconductor data sheet 16-bit proprietary microcontroller cmos f 2 mc-16lx mb90495g series mb90497g/f497g/f498g/v495g n description the mb90495g series is a general-purpose, high-performance 16-bit microcontroller. it was designed for devices like consumer electronics, which require high-speed, real-time process control. this series features an on-chip full-can interface. in addition to being backwards compatible with the f 2 mc* family architecture, the instruction set has been ex- panded to add support for high-level language instructions, expanded addressing mode, and enhanced multiply/ divide and bit processing instructions. a 32-bit accumulator is also provided, making it possible to process long word (32-bit) data. the mb90495g series peripheral resources include on chip 8/10-bit a/d converter, uart (sci) 0/1, 8/16-bit ppg timer, 16-bit i/o timer (16-bit free-run timer, input capture 0, 1, 2, 3 (icu) ) , and can controller. * : f 2 mc is abbreviation for fujitsu flexible microcontroller. f 2 mc is a registered trademark of fujitsu limited. n features ? models that support + 125 c ?clock ?built-in pll clock multiplier circuit ?choose 1/2 oscillation clock or 1 to 4 multiplied oscillation clock (for a 4-mhz oscillation clock, 4 to 16 mhz) machine (pll) clock (continued) n packages 64-pin plastic qfp 64-pin plastic lqfp (fpt-64p-m06) (fpt-64p-m09)
mb90495g series 2 (continued) ?select subclock behavior (8.192 khz) ?minimum instruction execution time : 62.5 ns (operating with 4-mhz oscillation clock and 4 pll clock) ? 16-mbyte cpu memory space ?24-bit internal addressing ?external access possible through selection of 8/16-bit bus width (external bus mode) ? optimum instruction set for controller applications ?wealth of data types (bit, byte, word, long word) ?wealth of addressing modes (23 different modes) ?enhanced signed multiply-divide instructions and reti instruction functions ?enhanced high-precision arithmetic employing 32-bit accumulator ? instruction set supports high-level programming language (c) and multitasking ?employs system stack pointer ?enhanced indirect instructions with all pointer types ?barrel shift instructions ? improved execution speed ?4-byte instruction queue ? powerful interrupt feature ?powerful 8-level, 34-condition interrupt feature ? cpu-independent automated data forwarding ?extended intelligent i/o service feature (ei 2 os) : maximum 16 channels ? low-power consumption (standby) mode ?sleep mode (cpu operation clock stopped) ?time-base timer mode (oscillation clock and subclock, time-base timer and watch timer only operational) ?watch mode (subclock and watch timer only operational) ?stop mode (oscillation clock and subclock stopped) ?cpu intermittent operation mode ? process ?cmos technology ? i/o ports ?generic i/o ports (cmos output) : 49 ?timer ?time-base timer, watch timer, watchdog timer : 1 channel ?8/16-bit ppg timer : four 8-bit channels, or two 16-bit channels ?16-bit reload timer : 2 channels ?16-bit i/o timer 16-bit free-run timer : 1 channel 16-bit input capture (icu) : 4 channels generates interrupt requests by latching onto the count value of the 16-bit free-run timer with pin input edge detection (continued)
mb90495g series 3 (continued) ? can controller : 1 channel ?can specifications conform to versions 2.0a and 2.0b ?8 on-chip message buffers ?forwarding rate 10 kbps to 1 mbps (with 16-mhz machine clock) ? uart0 (sci) /uart1 (sci) : 2 channels ?all with full duplex double buffer ?use clock-asynchronous or clock-synchronous serial forwarding ? dtp/external interrupt : 8 channels ?a module for launching extended intelligent i/o service (ei 2 os) and generating external interrupts through external output ? delayed interrupt generation module ?generates interrupt requests for switching tasks ? 8/10-bit a/d converter : 8 channels ?switch between 8-bit and 10-bit resolution ?launch through external trigger input ?conversion time : 6.13 m s (with 16-mhz machine clock, including sampling time) ? program batch function ?2-address pointer rom correction ? clock output function
mb90495g series 4 n product lineup * : the s2 dipswitch setting when using the mb2145-507 emulation baud. for details, see the mb2145-507 hardware manual (2.7 emulator power pin) . (continued) paarmeter part number mb90f497g mb90497g mb90f498g mb90v495g feature classification flash rom mask rom flash rom product evaluated rom size 64 kbytes 128 kbytes ? ram size 2 kbytes 6 kbytes process cmos package lqfp64 (width 0.65 mm) , qfp64 (width 1.0 mm) pga256 operating power 4.5 v to 5.5 v emulator power supply* ? none cpu functions number of instructions instruction bit length instruction length data bit length : 351 : 8-bit, 16-bit : 1 to 7 bytes : 1 bit, 8-bit, 16-bit minimum execution time : 62.5 ns (with 16-mhz machine clock) interrupt processing time : minimum 1.5 m s (with 16-mhz machine clock) low-power consumption (standby) mode sleep mode/watch mode/time-base timer mode/stop mode / cpu intermittent mode i/o ports general-purpose i/o ports (cmos output) : 49 time-base timer 18-bit free-run counter interrupt interval : 1.024 ms, 4.096 ms, 16.834 ms, 131.072 ms (with 4-mhz oscillation clock) watchdog timer reset generation intervals : 3.58 ms, 14.33 ms, 57.23 ms, 458.75 ms (with 4-mhz oscillation clock) 16-bit i/o timer 16-bit free-run timer number of channels : 1 interrupts from overflow generation input capture number of channels : 4 maintenance of free-run timer value through pin input (rising, falling or both edg- es) 16-bit reload timer number of channels : 2 16-bit reload timer operation count clock interval : 0.25 m s, 0.5 m s, 2.0 m s (with 16-mhz machine clock) external event count enabled watch timer 15-bit free-run counter interrupt intervals : 31.25 ms, 62.5 ms, 12 ms, 250 ms, 500 ms, 1.0 s, 2.0 s (with 8.192-khz subclock) 8/16-bit ppg timer number of channels : 2 (two 8-bit channels can be used) two 8-bit or one 16-bit channel ppg operation possible free interval, free duty pulse output possible count clock : 62.5 ns to 1 m s (with 16-mhz machine clock)
mb90495g series 5 (continued) n packages and corresponding products : available : not available note : see package dimensions for details. n product comparison memory size when evaluating with evaluation chips and other means, take careful note of the different between the evaluation chip and the chip actually used. take particular note of the following. ? while the mb90v495g does not feature an on-chip rom, the dedicated development tool can be used to achieve operation equivalent to a product with built-in rom. therefore, the rom size is configured by the development tool. ? on the mb90v495g, the ff4000 h to ffffff h image is only visible in the 00 bank, and the fe0000 h to ff3fff h is only visible in the fe and ff banks (configurable on development tool) . ? on the mb90f497g/f498g/497g, the ff4000 h to ffffff h image is visible in the 00 bank, and the ff0000 h to ff3fff h is visible only in the ff bank. parameter part number mb90f497g mb90497g mb90f498g mb90v495g delayed interrupt generation module module for delayed interrupt generation switching tasks used in real-time os dtp/external interrupt circuit number of inputs : 8 starting by rising edge, falling edge, h level input, or l level input, external interrupts or extended intelligent i/o service (ei 2 os) can be used 8/10-bit a/d converter number of channels : 8 resolution : set 10-bit or 8-bit conversion time : 6.13 m s (with 16-mhz machine clock, including sampling time) continuous conversion of multiple linked channels possible (up to 8 channels can be set) one-shot conversion mode : converts selected channel only once continuous conversion mode : converts selected channel continuously stop conversion mode : converts selected channel and suspends operation repeatedly uart0 (sci) number of channels : 1 clock-synchronous forwarding : 62.5 kbps to 2 mbps clock-asynchronous forwarding : 1,202 bps to 62,500 bps transmission can be performed by two-way serial transmission or by master/ slave connection uart1 (sci) number of channels : 1 clock-synchronous forwarding : 62.5 kbps to 2 mbps clock-asynchronous forwarding : 9,615 bps to 500 kbps transmission can be performed by two-way serial transmission or by master/ slave connection can compliant with can specification versions 2.0a and 2.0b send/receive message buffers : 8 forwarding bit rate : 10 kbps to 1 mbps (with 16-mhz machine clock) package mb90f497g mb90497g mb90f498g fpt-64p-m06 fpt-64p-m09
mb90495g series 6 n pin assignments ? fpt-64p-m06 (top view) (fpt-64p-m06) p44/rx p61/int1 p62/int2 p50/an0 p51/an1 p52/an2 p53/an3 p54/an4 p55/an5 p56/an6 p57/an7 av cc avr av ss p60/int0 x0a x1a p63/int3 md0 51 42 33 p30/sot0/ale v ss p27/int7/a23 p26/int6/a22 p25/int5/a21 p24/int4/a20 p23/tot1/a19 p22/tin1/a18 p21/tot0/a17 p20/tin0/a16 p17/ppg3/ad15 p16/ppg2/ad14 p15/ppg1/ad13 p14/ppg0/ad12 p13/in3/ad11 p12/in2/ad10 p11/in1/ad09 p10/in0/ad08 p07/ad07 1 10 19 52 58 64 p31/sck0/rd p32/sin0/wrl p33/wrh p34/hrq p35/hak v cc c p36/frck/rdy p37/adtg/clk p40/sin1 p41/sck1 p42/sot1 p43/tx p06/ad06 p05/ad05 p04/ad04 p03/ad03 p02/ad02 p01/ad01 p00/ad00 v ss x1 x0 md2 md1 rst 32 26 20
mb90495g series 7 ? fpt-64p-m09 (top view) (fpt-64p-m09) p61/int1 p62/int2 p50/an0 p51/an1 p52/an2 p53/an3 p54/an4 p55/an5 p56/an6 p57/an7 av cc avr av ss p60/int0 x0a x1a 48 40 33 p27/int7/a23 p26/int6/a22 p25/int5/a21 p24/int4/a20 p23/tot1/a19 p22/tin1/a18 p21/tot0/a17 p20/tin0/a16 p17/ppg3/ad15 p16/ppg2/ad14 p15/ppg1/ad13 p14/ppg0/ad12 p13/in3/ad11 p12/in2/ad10 p11/in1/ad09 p10/in0/ad08 1 8 16 49 57 64 v ss p30/sot0/ale p31/sck0/rd p32/sin0/wrl p33/wrh p34/hrq p35/hak v cc c p36/frck/rdy p37/adtg/clk p40/sin1 p41/sck1 p42/sot1 p43/tx p44/rx p07/ad07 p06/ad06 p05/ad05 p04/ad04 p03/ad03 p02/ad02 p01/ad01 p00/ad00 v ss x1 x0 md2 md1 rst md0 p63/int3 32 24 17
mb90495g series 8 n pin description (continued) pin no. pin name circuit type description m06 m09 21 p61 d general-purpose i/o port int1 functions as external interrupt input pin. set this to input port. 32 p62 d general-purpose i/o port int2 functions as external interrupt input pin. set this to input port. 4 to 11 3 to 10 p50 to p57 e general-purpose i/o port an0 to an7 functions as analog input port of a/d converter. this is enabled if analog input configuration is permitted. 12 11 av cc ? v cc power input pin of a/d converter. 13 12 avr ? reference voltage ( + ) input pin for the a/d converter.this voltage must not exceed v cc and av cc . reference voltage ( - ) is fixed to av ss . 14 13 av ss ? v ss power input pin of a/d converter. 15 14 p60 d general-purpose i/o port int0 functions as external interrupt input pin. set this to input port. 16 15 x0a a low-speed oscillation pin. perform pull-down processing if not connected to an oscillator. 17 16 x1a a low-speed oscillation pin. set to open if not connected to an oscillator. 18 17 p63 d general-purpose i/o port int3 functions as external interrupt input pin. set this to input port. 19 18 md0 c input pin for specifying operation mode. 20 19 rst b external reset input pin. 21 20 md1 c input pin for specifying operation mode. 22 21 md2 f input pin for specifying operation mode. 23 22 x0 a high-speed oscillation pin. 24 23 x1 a high-speed oscillation pin. 25 24 v ss ? power supply (0 v) input pin. 26 to 33 25 to 32 p00 to p07 d general-purpose i/o port only enabled in single-chip mode. ad00 to ad07 i/o pin for the lower 8-bit of the external address data bus. only enabled during external bus mode. 34 to 37 33 to 36 p10 to p13 d general-purpose i/o port. only enabled in single-chip mode. in0 to in3 functions as trigger input pin for input capture channels 0 to 3. set this to input port. ad08 to ad11 i/o pin for upper 4-bit of external address data bus. only enabled during external bus mode.
mb90495g series 9 (continued) (continued) pin no. pin name circuit type description m06 m09 38 to 41 37 to 40 p14 to p17 d general-purpose i/o port. only enabled in single-chip mode. ppg0 to ppg3 functions as output pin of ppg timer 01, 23. only valid if output configu- ration is enabled. ad12 to ad15 i/o pin for upper 4-bit of external address data bus. only enabled during external bus mode. 42 41 p20 d general-purpose i/o port. when the bits of high address control register (hacr) are set to 1 in ex- ternal bus mode, these pins function as general purpose i/o ports. tin0 functions as event input pin of tin0 reload timer 0. set this to input port. a16 output pin of external address bus (a16) . only valid when the bits of high address control register (hacr) are set to 0 in external bus mode. 43 42 p21 d general-purpose i/o port. when the bits of high address control register (hacr) are set to 1 in ex- ternal bus mode, these pins function as general purpose i/o ports. tot0 functions as event output pin of tot0 reload timer 0. only valid if output configuration enabled. a17 output pin of external address bus (a17) . only valid when the bits of high address control register (hacr) are set to 0 in external bus mode. 44 43 p22 d general-purpose i/o port. when the bits of high address control register (hacr) are set to 1 in ex- ternal bus mode, these pins function as general purpose i/o ports. tin1 functions as event input pin of tin1 reload timer 1. set this to input port. a18 output pin of external address bus (a18) . only valid when the bits of high address control register (hacr) are set to 0 in external bus mode. 45 44 p23 d general-purpose i/o port. when the bits of high address control register (hacr) are set to 1 in ex- ternal bus mode, these pins function as general purpose i/o ports. tot1 functions as event output pin for tot1 reload timer 1. only valid if output configuration enabled. a19 output pin for external address bus (a19) . only valid when the bits of high address control register (hacr) are set to 0 in external bus mode.
mb90495g series 10 (continued) (continued) pin no. pin name circuit type description m06 m09 46 to 49 45 to 48 p24 to p27 d general-purpose i/o port. when the bits of high address control register (hacr) are set to 1 in ex- ternal bus mode, these pins function as general purpose i/o ports. int4 to int7 functions as external interrupt input pin. set this to input port. a20 to a23 output pin for external address bus (a20 to a23) . only valid when the bits of high address control register (hacr) are set to 0 in external bus mode. 50 49 v ss ? power supply (0 v) input pin. 51 50 p30 d general-purpose i/o port. only enabled in single-chip mode. sot0 uart0 serial data output pin. only valid if uart0 serial data output configuration is enabled. ale address latch authorization output pin. only enabled during external bus mode. 52 51 p31 d general-purpose i/o port. only enabled in single-chip mode. sck0 uart0 serial clock i/o pin. only valid if uart0 serial clock i/o configuration is enabled. rd lead strobe output pin. only enabled during external bus mode. 53 52 p32 d general-purpose i/o port. sin0 uart0 serial data input pin. set this to input port. wrl write strobe output pin for lower 8-bit of data bus. only valid if wrl pin output is enabled, in external bus mode. 54 53 p33 d general-purpose i/o port. wrh write strobe output pin for upper 8-bit of data bus. only valid if external bus mode/16-bit bus mode/wrh pin output enabled. 55 54 p34 d general-purpose i/o port. hrq hold request input pin. only valid if hold input is enabled, in external bus mode. 56 55 p35 d general-purpose i/o port. hak hold addressing output pin. only valid if hold input is enabled, in external bus mode. 57 56 v cc ? power supply (5 v) input pin. 58 57 c ? capacity pin for power stabilization. please connect to an approximately 0.1 m f ceramic capacitor.
mb90495g series 11 (continued) pin no. pin name circuit type description m06 m09 59 58 p36 d general-purpose i/o port. frck functions as an external clock input pin for a frck 16-bit free-run timer. set this to input port. rdy external ready input pin. only valid if external ready input is enabled, in external bus mode. 60 59 p37 d general-purpose i/o port. adtg functions as a/d converter external trigger input pin. set this to input port. clk external clock output pin. only valid if external clock output is enabled, in external bus mode. 61 60 p40 d general-purpose i/o port. sin1 uart1 serial data input pin. set this to input port. 62 61 p41 d general-purpose i/o port. sck1 uart1 serial clock i/o pin. only valid if uart1 clock i/o configuration is enabled. 63 62 p42 d general-purpose i/o port. sot1 uart1 serial data output pin. only valid if uart1 serial data output configuration is enabled. 64 63 p43 d general-purpose i/o port. tx can transmission output pin. only valid if output configuration enabled. 164 p44 d general-purpose i/o port. rx can reception input pin. set this to input port.
mb90495g series 12 n i/o circuit type (continued) type circuit remarks a ? high speed oscillation feedback resistor : 1 m w approx. ? low speed oscillation feedback resistor : 10 m w approx. b ? hysteresis input with pull-up ? pull-up resistor : 50 k w approx. c ? hysteresis input d ? cmos hysteresis input ? cmos level output ? standby control available e ? cmos hysteresis input ? cmos level output ? doubles as analog input pin ? standby control available x1 clock input standby control signal x0 x1a x0a r r v cc hysteresis input r hysteresis input r v cc pch nch v ss i ol = 4 ma digital output digital output hysteresis input standby control r v cc pch nch v ss i ol = 4 ma digital output digital output hysteresis input standby control analog input
mb90495g series 13 (continued) type circuit remarks f ? hysteresis input with pull-down ? pull-down resistor : 50 k w approx. (except flash device) r r v ss hysteresis input
mb90495g series 14 n handling devices ? make sure you do not exceed the maximum rated values (in order to prevent latch-up) . ? cmos ic chips may suffer latch-up if a voltage higher than v cc or lower than v ss is applied to an input or output pin with other than mid or high current resistance; or voltage exceeding the rating is applied across v cc and v ss . ? latch-ups can dramatically increase the power supply current, causing thermal breakdown of the device. make sure that you do not exceed the maximum rated value of your device, in order to prevent a latch-up. ? when turning the analog power supply on or off, make sure that the analog power voltage (av cc , avr) and analog input voltages do not exceed the digital voltage (v cc ) . ? handling unused pins leaving unused input pins open may cause malfunctions and latch-ups, permanently damaging the device. prevent this by connecting it to a pull-up or pull-down resistor of no less than 2 k w . leave unused output pins open in output mode, or if in input mode, handle them in the same as input pins. ? notes on using external clock when using the external clock, drive pin x0 only, and leave pin x1 unconnected. see below for an example of external clock use. example external clock use ? notes on not using subclock if you do not connect pins x0a and x1a to an oscillator, use pull-down handling on the x0a pin, and leave the x1a pin open. ?power supply pins ? if your product has multiple v cc or v ss pins, pins of the same potential are internally connected in the device in order to avoid abnormal operation, including latch-up. however, you should make sure to connect the pins external power and ground lines, in order to lower unneeded emissions, prevent abnormal operation of strobe signals due to a rise in ground levels, and maintain total output current within rated levels. ? take care to connect the v cc and v ss pins of mb90495g series devices to power lines via the lowest possible impedance. ? it is recommended that you connect a bypass capacitor of approximately 0.1 m f between v cc and v ss near mb90495g series device pins. ? crystal oscillator circuit ? noise in the vicinity of x0 and x1 pins could cause abnormal operations in mb90495g series devices. make sure to provide bypass capacitors via the shortest possible distance from x0 and x1 pins, crystal oscillators (or ceramic resonators) , and ground lines. in addition, design your printed circuit boards so as to keep x0 and x1 wiring from crossing other wiring, if at all possible. ? it is strongly recommended that you provide printed circuit board artwork surrounding x0 and x1 pins within a grand area, as this should stabilize operation. x0 x1 open mb90495g series
mb90495g series 15 ? a/d converter power-up and analog input initiation sequence ? make sure to power up the a/d converter and analog input (pins an0 to an7) after turning on digital power (v cc ) . ? turn off digital power after turning off the a/d converter power supply and analog inputs. in this case, make sure that the voltage of avr does not exceed av cc (it is permissible to turn off analog and digital power simultaneously) . ? connecting unused a/d converter pins if you are not using the a/d converter, set unused pins to av cc = avr = v cc , av ss = v ss . ? notes for powering up ensure that the voltage step-up time (between 0.2 v and 2.7 v) at power-up is no less than 50 m s, in order to prevent malfunction in the built-in step-down circuit. ? initialization the device contains built-in registers which are only initialized by a power-on reset. cycle the power supply to initialize these registers. ? stabilizing the power supply make sure that the v cc power supply voltage is stable. even at the rated operating v cc power supply voltage, large, sudden changes in the voltage could cause malfunctions. as a standard for stable power supply, keep v cc ripples (peak-to-peak value) at commercial power frequencies (50 hz to 60 hz) to no more than 10 % of the power supply voltage, and momentary surges caused by switching the power supply and other events to more than 0.1 v/ms. ? if output from ports 0/1 becomes undefined after power is turned on, if the rst pin is set to h during step-down circuit stabilization standby (during power- on reset) , ports 0 and 1 output will be undefined. if the rst pin is set to l, ports 0 and 1 will go into a high impedance state. take careful note of the timing of events outlined in figures 1 and 2.
mb90495g series 16 ? figure 1 - timing chart of undefined output from ports 0 / 1 ( with rst pin set to h ) ? figure 2 - timing chart of high impedance state for ports 0 / 1 ( when rst pin is l ) v cc (power supply pin) ponr (power-on reset) signal rst (external asynchronous reset) signal rst (internal reset) signal oscillation clock signal ka (internal operating clock a) signal kb (internal operating clock b) signal port (port output) signal time in standby for oscillation to stabilize * 2 time in standby for step- down circuit to stabilize * 1 time of undefined output *1 : step-down circuit stabilization standby time : 2 17 /oscillation clock frequency (with 16-mhz oscillation clock frequency, about 8.19 ms) *2 : oscillation stabilization standby time : 2 18 /oscillation clock frequency (with 16-mhz oscillation clock frequency, about 16.36 ms) v cc (power supply pin) ponr (power-on reset) signal rst (external asynchronous reset) signal rst (internal reset) signal oscillation clock signal ka (internal operation clock a) signal kb (internal operating clock b) signal port (port output) signal time in standby for oscillation to stabilize * 2 step-down circuit stabilization standby time * 1 high impedance *1 : step-down circuit stabilization standby time : 2 17 /oscillation clock frequency (with 16-mhz oscillation clock frequency, about 8.19 ms) *2 : oscillation stabilization standby time : 2 18 /oscillation clock frequency (with 16-mhz oscillation clock frequency, about 16.38 ms)
mb90495g series 17 ? caution on operations during pll clock mode if the pll clock mode is selected in the microcontroller, it may attempt to continue the operation using the free- running frequency of the automatic oscillating circuit in the pll circuitry even if the oscillator is out of place or the clock input is stopped. performance of this operation, however, cannot be guaranteed. ? support for + + + + 125 c if used exceeding t a = + 105 c, be sure to contact us for reliability limitations.
mb90495g series 18 n block diagram ram rom/flash can uart1 uart0 x0, x1 rst x0a, x1a sot1 sck1 sin1 sot0 sck0 sin0 av cc av ss an0 to an7 avr adtg frck in0 to in3 rx tx ppg0 to ppg3 int0 to int7 tin0, tin1 tot0, tot1 ad00 to ad15 a16 to a23 ale rd wrl wrh hrq hak rdy clk clock control circuit watch timer time-base timer prescaler prescaler 8/10 bit a/d converter (8 ch) cpu f 2 mc-16lx core 16 bit free-run timer internal data bus input capture (4 ch) 16-bit ppg timer (2 ch) dtp/external interrupt circuit 16 bits reload timer (2 ch) external bus
mb90495g series 19 n memory map the memory access modes of the mb90495g series can be set to single chip mode, internal rom - external bus mode, and external rom - external bus mode. 1. memory allocation of the mb90495g the mb90495g series has 24-bit internal address bus and 24-bit external address bus output, enabling it to access up to 16 mbytes of external access memory. the enable/disable time of the rom mirror function is shown graphically in the memory map. 2. memory map note : when the internal rom is operational, the rom data in the upper address of bank 00 of the f 2 mc-16lx is visible in an image. this is called the rom mirror function, and takes advantage of the small c compiler model. with the f 2 mc-16lx, the lower 16-bit address of bank ff and the lower 16-bit address of bank 00 are set identical to one another. this allows the rom-internal table to be referenced without specifying a far pointer. for example, say the address 00c000 h is accessed. in actuality, the ffc000 h address inside rom will be accessed. however, as the rom space in bank ff exceeds 48 kbytes, the entire space cannot be viewed on bank 00s image. and so, since ff4000 h to ffffff h rom data will be visible on the 004000 h to 00ffff h image, save the rom data table in the ff4000 h to ffffff h space. address #3 000000 h 0000c0 h 000100 h 003900 h 010000 h ffffff h single chip mode (rom mirror function available) periphery periphery periphery ram space register ram space register ram space register extention io space extention io space extention io space rom space (image of bank ff) rom space (image of bank ff) rom space rom space internal rom external bus mode external rom external bus mode address #1 address #2 internal access memory external access memory access prohibited 003800 h 002000 h * : addresses #1 and #3 are product-specific. product address #1 * address #2 address #3 * mb90v495g 001900 h 004000 h (fc0000 h ) mb90f497g 000900 h 004000 h ff0000 h mb90497g 000900 h 004000 h ff0000 h mb90f498g 000900 h 004000 h fe0000 h
mb90495g series 20 n i/o map (continued) address register abbreviation register name access resource name initial value 000000 h pdr0 port 0 data register r/w port 0 xxxxxxxx b 000001 h pdr1 port 1 data register r/w port 1 xxxxxxxx b 000002 h pdr2 port 2 data register r/w port 2 xxxxxxxx b 000003 h pdr3 port 3 data register r/w port 3 xxxxxxxx b 000004 h pdr4 port 4 data register r/w port 4 xxxxxxxx b 000005 h pdr5 port 5 data register r/w port 5 xxxxxxxx b 000006 h pdr6 port 6 data register r/w port 6 xxxxxxxx b 000007 h to 00000f h (system-reserved area) * 000010 h ddr0 port 0 direction register r/w port 0 0 0 0 0 0 0 0 0 b 000011 h ddr1 port 1 direction register r/w port 1 0 0 0 0 0 0 0 0 b 000012 h ddr2 port 2 direction register r/w port 2 0 0 0 0 0 0 0 0 b 000013 h ddr3 port 3 direction register r/w port 3 0 0 0 0 0 0 0 0 b 000014 h ddr4 port 4 direction register r/w port 4 xxx 0 0 0 0 0 b 000015 h ddr5 port 5 direction register r/w port 5 0 0 0 0 0 0 0 0 b 000016 h ddr6 port 6 direction register r/w port 6 xxxx 0 0 0 0 b 000017 h to 00001a h ( system - reserved area ) * 00001b h ader analog input enable register r/w 8/10-bit a/d converter 1 1 1 1 1 1 1 1 b 00001c h to 00001f h (system-reserved area) * 000020 h smr0 serial mode register 0 r/w uart0 0 0 0 0 0 0 0 0 b 000021 h scr0 serial control register 0 r/w 0 0 0 0 0 1 0 0 b 000022 h sidr0/ sodr0 serial input data register 0/ serial output data register 0 r/w xxxxxxxx b 000023 h ssr0 serial status register 0 r/w 0 0 0 0 1 x 0 0 b 000024 h cdcr0 communication prescaler control register 0 r/w 0 xxx 1 1 1 1 b 000025 h ses0 serial edge selection register 0 r/w xxxxxxx 0 b 000026 h smr1 serial mode register 1 r/w uart1 0 0 0 0 0 0 0 0 b 000027 h scr1 serial control register 1 r/w 0 0 0 0 0 1 0 0 b 000028 h sidr1/ sodr1 serial input data register 1/ serial output data register 1 r/w xxxxxxxx b
mb90495g series 21 (continued) (continued) address register abbreviation register name access resource name initial value 000029 h ssr1 serial status register 1 r/w uart1 0 0 0 0 1 0 0 0 b 00002a h (system-reserved area) * 00002b h cdcr1 communication prescaler control register 1 r/w uart1 0 xxx 0 0 0 0 b 00002c h to 00002f h (system-reserved area) * 000030 h enir dtp/external interrupt enable register r/w dtp/external interrupt 0 0 0 0 0 0 0 0 b 000031 h eirr dtp/external interrupt condition register r/w xxxxxxxx b 000032 h elvr detection level configuration register r/w 0 0 0 0 0 0 0 0 b 000033 h r/w 0 0 0 0 0 0 0 0 b 000034 h adcs a/d control status register r/w 8/10-bit a/d converter 0 0 0 0 0 0 0 0 b 000035 h r/w 0 0 0 0 0 0 0 0 b 000036 h adcr a/d data register r xxxxxxxx b 000037 h r/w 0 0 1 0 1 xxx b 000038 h to 00003f h ( system - reserved area ) * 000040 h ppgc0 ppg0 operation mode control register r/w 8/16-bit ppg timer 0/1 0 x 0 0 0 xx 1 b 000041 h ppgc1 ppg1 operation mode control register r/w 0 x 0 0 0 0 0 1 b 000042 h ppg01 ppg0/1 count clock selection register r/w 0 0 0 0 0 0 xx b 000043 h (system-reserved area) * 000044 h ppgc2 ppg2 operation mode control register r/w 8/16-bit ppg timer 2/3 0 x 0 0 0 xx 1 b 000045 h ppgc3 ppg3 operation mode control register r/w 0 x 0 0 0 0 0 1 b 000046 h ppg23 ppg2/3 count clock selection register r/w 0 0 0 0 0 0 xx b 000047 h to 00004f h (system-reserved area) * 000050 h ipcp0 input capture data register 0 r 16-bit i/o timer xxxxxxxx b 000051 h xxxxxxxx b 000052 h ipcp1 input capture data register 1 r xxxxxxxx b 000053 h xxxxxxxx b 000054 h ics01 input capture control status register r/w 0 0 0 0 0 0 0 0 b 000055 h ics23 0 0 0 0 0 0 0 0 b 000056 h tcdt timer counter data register r/w 0 0 0 0 0 0 0 0 b 000057 h 0 0 0 0 0 0 0 0 b
mb90495g series 22 (continued) (continued) address register abbreviation register name access resource name initial value 000058 h tccs timer counter control status register r/w 16-bit i/o timer 0 0 0 0 0 0 0 0 b 000059 h 0 xxxxxxx b 00005a h ipcp2 input capture data register 2 r xxxxxxxx b 00005b h xxxxxxxx b 00005c h ipcp3 input capture data register 3 r xxxxxxxx b 00005d h xxxxxxxx b 00005e h to 000065 h (system-reserved area) * 000066 h tmcsr0 timer control status register r/w 16-bit reload timer 0 0 0 0 0 0 0 0 0 b 000067 h r/w xxxx0 0 0 0 b 000068 h tmcsr1 r/w 16-bit reload timer 1 0 0 0 0 0 0 0 0 b 000069 h r/w xxxx0 0 0 0 b 00006a h to 00006e h (system-reserved area) * 00006f h romm rom mirror function selection register w rom mirror function selection module xxxxxxx 1 b 000070 h to 00007f h (system-reserved area) * 000080 h bvalr message buffer valid register r/w can controller 0 0 0 0 0 0 0 0 b 000081 h (system-reserved area) * 000082 h treqr send request register r/w can controller 0 0 0 0 0 0 0 0 b 000083 h (system-reserved area) * 000084 h tcanr send cancel register w can controller 0 0 0 0 0 0 0 0 b 000085 h (system-reserved area) * 000086 h tcr send complete register r/w can controller 0 0 0 0 0 0 0 0 b 000087 h (system-reserved area) * 000088 h rcr reception complete register r/w can controller 0 0 0 0 0 0 0 0 b 000089 h (system-reserved area) * 00008a h rrtrr reception rtr register r/w can controller 0 0 0 0 0 0 0 0 b 00008b h (system-reserved area) * 00008c h rovrr reception overrun register r/w can controller 0 0 0 0 0 0 0 0 b 00008d h (system-reserved area) * 00008e h rier reception complete interrupt enable register r/w can controller 0 0 0 0 0 0 0 0 b
mb90495g series 23 (continued) (continued) address register abbreviation register name access resource name initial value 00008f h to 00009d h (system-reserved area) * 00009e h pacsr address detection control register r/w rom correction function 0 0 0 0 0 0 0 0 b 00009f h dirr delayed interrupt request generate/ cancel register r/w delayed interrupt generation module xxxxxxx 0 b 0000a0 h lpmcr low power consumption mode control register r/w low-power consumption modes 0 0 0 1 1 0 0 0 b 0000a1 h ckscr clock selection register r/w clock 1 1 1 1 1 1 0 0 b 0000a2 h to 0000a4 h (system-reserved area) * 0000a5 h arsr auto ready function selection register w external access 0 0 1 1 xx 0 0 b 0000a6 h hacr high address control register w 0 0 0 0 0 0 0 0 b 0000a7 h ecsr bus control signal selection register w 0 0 0 0 0 0 0 x b or 0 0 0 0 1 0 0 x b 0000a8 h wdtc watchdog timer control register r/w watchdog timer xxxxx 1 1 1 b 0000a9 h tbtc time-base timer control register r/w time-base timer 1 xx 0 0 1 0 0 b 0000aa h wtc watch timer control register r/w watch timer 1 0 0 0 1 0 0 0 b 0000ab h to 0000ad h (system-reserved area) * 0000ae h fmcs flash memory control status register r/w 512-kbit flash memory 0 0 0 x 0 0 0 0 b 0000af h (system-reserved area) * 0000b0 h icr00 interrupt control register 00 r/w interrupt controller 0 0 0 0 0 1 1 1 b 0000b1 h icr01 interrupt control register 01 r/w 0 0 0 0 0 1 1 1 b 0000b2 h icr02 interrupt control register 02 r/w 0 0 0 0 0 1 1 1 b 0000b3 h icr03 interrupt control register 03 r/w 0 0 0 0 0 1 1 1 b 0000b4 h icr04 interrupt control register 04 r/w 0 0 0 0 0 1 1 1 b 0000b5 h icr05 interrupt control register 05 r/w 0 0 0 0 0 1 1 1 b 0000b6 h icr06 interrupt control register 06 r/w 0 0 0 0 0 1 1 1 b 0000b7 h icr07 interrupt control register 07 r/w 0 0 0 0 0 1 1 1 b 0000b8 h icr08 interrupt control register 08 r/w 0 0 0 0 0 1 1 1 b 0000b9 h icr09 interrupt control register 09 r/w 0 0 0 0 0 1 1 1 b 0000ba h icr10 interrupt control register 10 r/w 0 0 0 0 0 1 1 1 b
mb90495g series 24 (continued) (continued) address register abbreviation register name access resource name initial value 0000bb h icr11 interrupt control register 11 r/w interrupt controller 0 0 0 0 0 1 1 1 b 0000bc h icr12 interrupt control register 12 r/w 0 0 0 0 0 1 1 1 b 0000bd h icr13 interrupt control register 13 r/w 0 0 0 0 0 1 1 1 b 0000be h icr14 interrupt control register 14 r/w 0 0 0 0 0 1 1 1 b 0000bf h icr15 interrupt control register 15 r/w 0 0 0 0 0 1 1 1 b 0000c0 h to 0000ff h (system-reserved area) * 001ff0 h padr0 detection address configuration register 0 (lower) r/w rom correction function xxxxxxxx b 001ff1 h detection address configuration register 0 (mid) r/w xxxxxxxx b 001ff2 h detection address configuration register 0 (upper) r/w xxxxxxxx b 001ff3 h padr1 detection address configuration register 1 (lower) r/w xxxxxxxx b 001ff4 h detection address configuration register 1 (mid) r/w xxxxxxxx b 001ff5 h detection address configuration register 1 (upper) r/w xxxxxxxx b 003900 h tmr0/ tmrlr0 16-bit timer register 0/ 16-bit reload register 0 r/w 16-bit reload timer 0 xxxxxxxx b 003901 h xxxxxxxx b 003902 h tmr1/ tmrlr1 16-bit timer register 1/ 16 - bit reload register 1 r/w 16-bit reload timer 1 xxxxxxxx b 003903 h xxxxxxxx b 003904 h to 00390f h ( system - reserved area ) * 003910 h prll0 ppg0 reload register l r/w 8/16-bit ppg timer xxxxxxxx b 003911 h prlh0 ppg0 reload register h r/w xxxxxxxx b 003912 h prll1 ppg1 reload register l r/w xxxxxxxx b 003913 h prlh1 ppg1 reload register h r/w xxxxxxxx b 003914 h prll2 ppg2 reload register l r/w xxxxxxxx b 003915 h prlh2 ppg2 reload register h r/w xxxxxxxx b 003916 h prll3 ppg3 reload register l r/w xxxxxxxx b 003917 h prlh3 ppg3 reload register h r/w xxxxxxxx b 003918 h to 003bff h (system-reserved area) * 003c00 h to 003c0f h ram (general-purpose ram)
mb90495g series 25 (continued) (continued) address register abbreviation register name access resource name initial value 003c10 h to 003c13 h idr0 id register 0 r/w can controller xxxxxxxx b to xxxxxxxx b 003c14 h to 003c17 h idr1 id register 1 r/w xxxxxxxx b to xxxxxxxx b 003c18 h to 003c1b h idr2 id register 2 r/w xxxxxxxx b to xxxxxxxx b 003c1c h to 003c1f h idr3 id register 3 r/w xxxxxxxx b to xxxxxxxx b 003c20 h to 003c23 h idr4 id register 4 r/w xxxxxxxx b to xxxxxxxx b 003c24 h to 003c27 h idr5 id register 5 r/w xxxxxxxx b to xxxxxxxx b 003c28 h to 003c2b h idr6 id register 6 r/w xxxxxxxx b to xxxxxxxx b 003c2c h to 003c2f h idr7 id register 7 r/w xxxxxxxx b to xxxxxxxx b 003c30 h 003c31 h dlcr0 dlc register 0 r/w xxxxxxxx b xxxxxxxx b 003c32 h 003c33 h dlcr1 dlc register 1 r/w xxxxxxxx b xxxxxxxx b 003c34 h 003c35 h dlcr2 dlc register 2 r/w xxxxxxxx b xxxxxxxx b 003c36 h 003c37 h dlcr3 dlc register 3 r/w xxxxxxxx b xxxxxxxx b 003c38 h 003c39 h dlcr4 dlc register 4 r/w xxxxxxxx b xxxxxxxx b 003c3a h 003c3b h dlcr5 dlc register 5 r/w xxxxxxxx b xxxxxxxx b 003c3c h 003c3d h dlcr6 dlc register 6 r/w xxxxxxxx b xxxxxxxx b 003c3e h 003c3f h dlcr7 dlc register 7 r/w xxxxxxxx b xxxxxxxx b 003c40 h to 003c47 h dtr0 data register 0 r/w xxxxxxxx b to xxxxxxxx b
mb90495g series 26 (continued) (continued) address register abbreviation register name access resource name initial value 003c48 h to 003c4f h dtr1 data register 1 r/w can controller xxxxxxxx b to xxxxxxxx b 003c50 h to 003c57 h dtr2 data register 2 r/w xxxxxxxx b to xxxxxxxx b 003c58 h to 003c5f h dtr3 data register 3 r/w xxxxxxxx b to xxxxxxxx b 003c60 h to 003c67 h dtr4 data register 4 r/w xxxxxxxx b to xxxxxxxx b 003c68 h to 003c6f h dtr5 data register 5 r/w xxxxxxxx b to xxxxxxxx b 003c70 h to 003c77 h dtr6 data register 6 r/w xxxxxxxx b to xxxxxxxx b 003c78 h to 003c7f h dtr7 data register 7 r/w xxxxxxxx b to xxxxxxxx b 003c80 h to 003cff h ( system - reserved area ) * 003d00 h 003d01 h csr control status register r/w can controller 0 xxxx 0 0 1 b 0 0 xxx 0 0 0 b 003d02 h leir display last event register r/w 0 0 0 xx 0 0 0 b 003d03 h (system-reserved area) * 003d04 h 003d05 h rtec receive/transmit error counter r can controller 0 0 0 0 0 0 0 0 b 0 0 0 0 0 0 0 0 b 003d06 h 003d07 h btr bit timing register r/w 1 1 1 1 1 1 1 1 b x 1 1 1 1 1 1 1 b 003d08 h ider ide register r/w xxxxxxxx b 003d09 h (system-reserved area) * 003d0a h trtrr transmit rtr register r/w can controller 0 0 0 0 0 0 0 0 b 003d0b h (system-reserved area) * 003d0c h rfwtr remote frame reception standby register r/w can controller xxxxxxxx b 003d0d h (system-reserved area) * 003d0e h tier transmit complete interrupt enable register r/w can controller 0 0 0 0 0 0 0 0 b
mb90495g series 27 (continued) explanation of reset values 0 : the reset value of this bit is 0. 1 : the reset value of this bit is 1. x : the reset value of this bit is undefined. * : system-reserved area contains system-internal addresses, and cannot be used. address register abbreviation register name access resource name initial value 003d0f h (system-reserved area) * 003d10 h 003d11 h amsr acceptance mask selection register r/w can controller xxxxxxxx b xxxxxxxx b 003d12 h 003d13 h (system-reserved area) * 003d14 h to 003d17 h amr0 acceptance mask register 0 r/w can controller xxxxxxxx b to xxxxxxxx b 003d18 h to 003d1b h amr1 acceptance mask register 1 r/w xxxxxxxx b to xxxxxxxx b 003d1c h to 003fff h (system-reserved area) *
mb90495g series 28 n interrupt conditions and interrupt vector/register (continued) interrupt condition ei 2 os compatible interrupt vector interrupt register priority * 3 number address icr address reset #08 08 h ffffdc h ?? highest int 9 instruction #09 09 h ffffd8 h ?? - exception processing #10 0a h ffffd4 h ?? can controller reception complete (rx) #11 0b h ffffd0 h icr00 0000b0 h (* 1 ) can controller reception complete (tx) /node status transition (ns) #12 0c h ffffcc h reserved #13 0d h ffffc8 h icr01 0000b1 h reserved #14 0e h ffffc4 h external interrupt (int0/int1) #15 0f h ffffc0 h icr02 0000b2 h (* 1 ) time-base timer #16 10 h ffffbc h 16-bit reload timer 0 #17 11 h ffffb8 h icr03 0000b3 h (* 1 ) 8/10-bit a/d converter #18 12 h ffffb4 h 16-bit free-run timer overflow #19 13 h ffffb0 h icr04 0000b4 h (* 1 ) external interrupt (int2/int3) #20 14 h ffffac h reserved #21 15 h ffffa8 h icr05 0000b5 h (* 2 ) ppg timer ch0, ch1 underflow #22 16 h ffffa4 h input capture 0 load #23 17 h ffffa0 h icr06 0000b6 h (* 1 ) external interrupt (int4/int5) #24 18 h ffff9c h input capture 1 load #25 19 h ffff98 h icr07 0000b7 h (* 1 ) ppg timer ch2, ch3 underflow #26 1a h ffff94 h external interrupt (int6/int7) #27 1b h ffff90 h icr08 0000b8 h (* 1 ) watch timer #28 1c h ffff8c h reserved #29 1d h ffff88 h icr09 0000b9 h (* 1 ) input capture 2 load input capture 3 load #30 1e h ffff84 h reserved #31 1f h ffff80 h icr10 0000ba h (* 1 ) reserved #32 20 h ffff7c h reserved #33 21 h ffff78 h icr11 0000bb h (* 1 ) reserved #34 22 h ffff74 h reserved #35 23 h ffff70 h icr12 0000bc h (* 1 ) 16-bit reload timer 1 #36 24 h ffff6c h uart1 reception complete #37 25 h ffff68 h icr13 0000bd h (* 1 ) uart1 transmission complete #38 26 h ffff64 h
mb90495g series 29 (continued) : available : not available : available, ei 2 os halt function supplied : available for interrupt conditions not shared by icr *1 : the interrupt level is the same for peripheral devices sharing the icr register. peripheral devices that share the icr register and use the extended intelligent i/o service only utilize one set. if one side of a peripheral device sharing the icr register is set to extended intelligent i/o service, the other side cannot use interrupts. *2 : only the 16-bit reload timer is compatible with ei 2 os. since ppg does not support ei 2 os, if you use ei 2 os with the 16-bit reload timer, prohibit interrupts by ppg. *3 : priority if two or more interrupts with the same level are generated simultaneously. interrupt condition ei 2 os compatible interrupt vector interrupt register priority * 3 number address icr address uart0 reception complete #39 27 h ffff60 h icr14 0000be h (* 1 ) uart0 transmission complete #40 28 h ffff5c h flash memory #41 29 h ffff58 h icr15 0000bf h (* 1 ) delayed interrupt generation module #42 2a h ffff54 h lowest
mb90495g series 30 n peripheral resources 1. i/o port (1) overview general-purpose (parallel) i/o ports can be used as the i/o ports. the mb90495g series has 7 ports (49) . each port doubles as a peripheral device i/o pin. ? i/o port features i/o ports output data to i/o pins and load signals input to them, by means of the port data register (pdr) . additionally, the port direction register (ddr) sets the i/o direction of the i/o pins at the bit level. below is a description of each pins function, and the peripheral device that shares it. ? port 0 : general-purpose i/o port/doubles as external address data bus pin ? port 1 : general-purpose i/o port/doubles as ppg timer output, input capture input, and external address data bus pin ? port 2 : general-purpose i/o port/doubles as reload timer i/o, external interrupt input pin, and external address bus pin ? port 3 : general-purpose i/o port/doubles as uart0 i/o, free-run timer, and a/d converter startup trigger pin ? port 4 : general-purpose i/o port/doubles as uart1 i/o, and can controller transmit/receive pin ? port 5 : general-purpose i/o port/doubles as analog input pin ? port 6 : general-purpose i/o port/doubles as external interrupt input pin
mb90495g series 31 ? pin block diagram for port 0 ( single chip mode ) ? port 0 register (single chip mode) ? the port 0 register contains the port 0 data register (pdr0) and the port 0 direction register (ddr0) . ? the bits making up the register are in a one-to-one relation to the port 0 pin. compatibility between port 0 register and pin port name related register bit and corresponding pin port 0 pdr0, ddr0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 corresponding pin p07 p06 p05 p04 p03 p02 p01 p00 pch nch internal data bus pdr (port data register) ddr (port direction register) pdr read pdr write output latch direction latch ddr write ddr read pin standby control (spl = 1) standby control : control stop mode (spl = 1) , time-base timer mode (spl = 1) and watch mode (spl = 1)
mb90495g series 32 ? block diagram for pins of ports 1, 2, 3 and 4 (single-chip mode) ? port 1 register (single-chip mode) ? the port1 register contains the port 1 data register (pdr1) and the port 1 direction register (ddr1) . ? the bits making up the register are in a one-to-one relationship with the port 1 pins. port 1 register and corresponding pins port name related register bit and corresponding pin port 1 pdr1, ddr1 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 corresponding pin p17 p16 p15 p14 p13 p12 p11 p10 pch nch internal data bus peripheral device input peripheral device output port data register (pdr) pdr read pdr write output latch peripheral device output enabled pin port direction register (ddr) direction latch ddr write ddr read standby control (spl = 1) standby control : control stop mode (spl = 1) , time-base timer mode (spl = 1) and watch mode (spl = 1)
mb90495g series 33 ? port 2 register ? the port2 register contains the port 2 data register (pdr2) , the port 2 direction register (ddr2) and the high address control register (hacr). ? the high address control register (hacr) enables or disables the output of external addresses (a 16 to a 23 ). when the register enables the output of the external addresses, the port can not be used as a peripheral device and a general-purpose i/o port. ? the bits making up the register are in a one-to-one relationship with the port 2 pins. port 2 register and corresponding pins ? port 3 register ? the port3 register contains the port 3 data register (pdr3) and the port 3 direction register (ddr3) . ? the bus control signal selection register (ecsr) enables or disables the input and output of external bus control signals (wrl / wrh , hrq / hak , rdy, clk). when the register enables the input and output of the external bus control signals, the port can not be used as a peripheral device and a general-purpose i/o port. ? the bits making up the register are in a one-to-one relationship with the port 3 pins. port 3 register and corresponding pins ? port 4 register ? the port4 register contains the port 4 data register (pdr4) and the port 4 direction register (ddr4) . ? the bits making up the register are in a one-to-one relationship with the port 4 pins. port 4 register and corresponding pins port name related register bit and corresponding pin port 2 pdr2, ddr2, hacr bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 corresponding pin p27 p26 p25 p24 p23 p22 p21 p20 port name related register bit and corresponding pin port 3 pdr3, ddr3 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 ecsr cke rye hde wre ? corresponding pin p37 p36 p35 p34 p33 p32 p31 p30 port name related register bit and corresponding pin port 4 pdr4, ddr4 ??? bit4 bit3 bit2 bit1 bit0 corresponding pin ??? p44 p43 p42 p41 p40
mb90495g series 34 ? block diagram of port 5 pins ? port 5 register ? the port 5 register contains the port 5 data register (pdr5) , the port 5 direction register (ddr5) and the analog input enable register (ader) . ? the analog data enable register (ader) enables or disables the input of analog signals by the analog input pin. ? the bits making up the register are in a one-to-one correspondence with the pins of port 5. port 5 register and corresponding pins port name related register bit and corresponding pin port 5 pdr5, ddr5 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 ader ade7 ade6 ade5 ade4 ade3 ade2 ade1 ade0 corresponding pin p57 p56 p55 p54 p53 p52 p51 p50 ader pch nch internal data bus port data register (pdr) port direction register (ddr) pdr read pdr write analog input output latch direction latch pin ddr write ddr read standby control (spl = 1) standby control : control stop mode (spl = 1) , time-base timer mode (spl = 1) , and watch mode (spl = 1)
mb90495g series 35 ? block diagram of port 6 pins ? port 6 register ? the port 6 register contains the port 6 data register (pdr6) and the port 6 direction register (ddr6) . ? the bits making up the register are in a one-to-one relationship with the port 6 pins. port 6 register and corresponding pins port name related register bit and corresponding pin port 6 pdr6, ddr6 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 corresponding pin ???? p63 p62 p61 p60 pch nch internal data bus peripheral device input port data register (pdr) pdr read output latch pdr write port direction register (ddr) direction latch ddr write ddr read pin standby control (spl = 1) standby control : control stop mode (spl = 1) , time-base timer mode (spl = 1) , and watch mode (spl = 1)
mb90495g series 36 2. time-base timer the time-base timer is an 18-bit free-run counter (time-base counter) for counting up in synchronization with the main clock (1/2 main oscillation clock) . ? four interval times are available, and interrupt requests can be generated for each interval time. ? the time-base timer also has a function for supplying timers for oscillation stabilize standby time and operating clocks for peripheral devices. ? interval timer feature ? when the time-base timer counter reaches the interval set by the interval time selection bits (tbtc : tbc1, tbc0) , it generates an overflow (tbtc : tbof = 1) and interrupt request. ? if the interrupts due to overflow generation are enabled (tbtc : tbie = 1) , when an overflow is generated (tbtc : tbof = 1) , an interrupt is generated. ? select from the following 4 time-base timer intervals : time-base timer interval times hclk : oscillation clock the number in parentheses ( ) for 4-mhz oscillation clock operation ? time-base timer block diagram see below for the actual interrupt request number of the time-base timer : interrupt request number : #16 (10 h ) count clock interval time 2/hclk (0.5 m s) 2 12 /hclk (approx. 1.0 ms) 2 14 /hclk (approx. 4.1 ms) 2 16 /hclk (approx. 16.4 ms) 2 19 /hclk (approx. 131.1 ms) tbie ? ? tbof tbr tbc1 tbc0 2 1 2 1/ hclk 2 2 2 3 2 8 2 9 2 10 2 11 2 12 2 13 2 14 2 15 2 16 2 17 2 18 of of of of to ppg timer time-base timer counter to watchdog timer to clock controller oscillation stabilize standby time selector interval timer selector set tbof clear tbof clear counter circuit power-on reset ckscr : mcs = 1 ? 0* 1 ckscr : scs = 0 ? 1* 2 stop mode time-base timer control register (tbtc) time-base timer interrupt signal re- served of : overflow hclk : oscillation clock *1 : switch machine clock from main clock to pll clock *2 : switch machine clock from subclock to main clock
mb90495g series 37 3. watchdog timer the watchdog timer is a 2-bit timer used as a count clock for the timer-based or watch timer. if the counter is not cleared within the interval time, it resets the cpu. ? watchdog timer function ? the watchdog timer is a timer counter used to deal with runaway programs. once the watchdog timer is launched, it is necessary to keep clearing its counter within the specified interval. if the specified interval passes without the watchdog timer counter being cleared, the cpu will be reset. this feature is called the watchdog timer. ? the watchdog timer interval traces back to the clock interval input as the count clock. a watchdog reset is generated for the smallest to largest times. ? the clock source output destination is set by the watchdog clock selection bit of the watch timer control register (wtc : wdcs) . ? the watchdog timer interval is set time-base timer output selection bit/watch timer output selection bit of the watchdog timer control register (wdtc : wt1, wt0) . watchdog timer intervals hclk : oscillation clock (4 mhz) ; sclk : subclock (8.192 khz) notes: if the count clock of the watchdog timer is set to time-base timer output (overflow signal) , then clearing the time-base timer could make it take longer to reset the watchdog. if you are using a subclock as the machine clock, make sure to select watch timer output by setting the watchdog timer clock source selection bit (wdcs) of the watch timer control register (wtc) to 0. minimum maximum clock interval minimum maximum clock interval approx. 3.58 ms approx. 4.61 ms 2 14 2 11 /hclk approx. 0.457 s approx. 0.576 s 2 12 2 9 /sclk approx. 14.33 ms approx. 18.3 ms 2 16 2 13 /hclk approx. 3.584 s approx. 4.608 s 2 15 2 12 /sclk approx. 57.23 ms approx. 73.73 ms 2 18 2 15 /hclk approx. 7.168 s approx. 9.216 s 2 16 2 13 /sclk approx. 458.75 ms approx. 589.82 ms 2 21 2 18 /hclk approx. 14.336 s approx. 18.432 s 2 17 2 14 /sclk
mb90495g series 38 ? watchdog timer block diagram ponr ? wrst erst srst wte wt1 wt0 wdcs 2 1 2 2 2 8 2 9 2 10 2 11 2 12 2 13 2 14 2 15 2 16 2 17 2 18 2 4 2 1 2 2 2 5 2 6 2 7 2 8 2 9 2 10 2 11 2 12 2 13 2 14 2 15 4 watchdog timer control register (wdtc) watchdog timer counter clearcontrol circuit (time-base timer counter) (clock counter) counter clock selector launch 2-bit counter clear watch timer control register (wtc) watchdog reset generation circuit to internal reset generation circuit reset generation go to sleep mode go to time-base timer mode go to watch mode go to stop mode main clock (1/2 hclk) subclock sclk hclk : oscillation clock sclk : subclock
mb90495g series 39 4. 16-bit i/o timer the 16-bit i/o timer is a complex module comprising one 16-bit free-run timer, and two input capture units (4 input pins) . clock interval input signals and pulse widths can be measured based on the 16-bit free-run timer. ? 16-bit i/o timer configuration the 16 - bit i / o timer is made up of the following modules : ? one 16-bit free-run timer ? two input capture units (each unit having 2 input pins) ? 16-bit i/o timer function (1) 16-bit free-run timer function the 16-bit free-run timer consists of a 16-bit up counter, a time counter control status register, and prescaler. the 16-bit up counter counts up in synchronization with a fraction of the machine clock. ? the count clock can be set to one of eight fractions of the machine clock. the external clock signals input to the 16-bit free-run timer clock input pin (frck) can be used as the count clock. ? interrupts can be generated in response to counter value overflows. ? interrupts launch the extended intelligent i/o service (ei 2 os) . ? the count value of the 16-bit free-run timer can be cleared to 0000 h by either a reset, or software clear via the timer count clear bit (tccs : clr) . ? the count value of the 16-bit free-run timer is output to the input capture, and used as the base time for capture operation. (2) input capture function when the input capture detects that an external signal edge has been input to an input pin, it stores the count value of the 16-bit free-run timer in the input capture data register, for the point at which the edge was detected. the input capture consists of an input capture register corresponding to four i/o pins, an input capture control status register, and an edge detection circuit. ? when an edge is detected, either rising, falling, or both can be selected. ? an interrupt request can be generated to the cpu when an input signal edge is detected. ? interrupts launch the extended intelligent i/o service (ei 2 os) . ? since the input capture has four pairs of input pins and input capture data registers, it can measure up to 4 phenomena. ? block diagram of 16-bit i/o timer internal data bus input capture dedicated bus 16-bit free-run timer 16-bit free-run timer: the counter value of the 16-bit free-run timer is used as the base time of the input capture. input capture: input capture detects rising, falling and both edges for external signals input to input pins, and stores the counter value of the 16-bit free-run timer. interrupts can be generated in response to input signal edge detection.
mb90495g series 40 ? block diagram of 16 - bit free - run timer ivf ivfe stop clr clk2 clk1 clk0 of frck 2 f stop clk clr pin prescaler timer counter control status register (tccs) timer counter data register (tcdt) 16-bit free-run timer re- served output count value to input capture internal data bus free-run timer interrupt request note: the 16-bit i/o timer contains one 16-bit free-run timer. the interrupt request number of the 16-bit free-run timer is as follows : interrupt request number : 19 (13 h ) prescaler: takes a fraction of the machine clock, and supplies a count clock to the 16-bit up-counter. one of four machine clock fractions can be selected by setting the timer counter control status register (tccs) . timer counter register (tcdt) : this is a 16-bit up-counter. it is possible to read the current counter value of the 16-bit free-run timer by reading this counter. the counter can be set to an arbitrary value by writing to it while stopped. timer counter control status register (tccs) : tccs selects the divide ratio of a machine clock, executes software clear of counter values. and enables or disables counter operation. also tccs confirms and clears an overflow generation flag, and enables or disables interruption. f : machine clock of : overflow
mb90495g series 41 ? input capture block diagram icp1 icp0 ice1 ice0 eg11eg10eg01eg00 2 2 in3 in2 icp1 icp0 ice1 ice0 eg11eg10eg01eg00 2 2 in1 in0 edge detection circuit pin pin pin pin input capture control status register (ics23) input capture control status register (ics01) edge detection circuit 16-bit free-run timer input capture data register 3 (ipcp3) input capture data register 2 (ipcp2) input capture interrupt request input capture data register 1 (ipcp1) input capture data register 0 (ipcp0) internal data bus
mb90495g series 42 5. 16-bit reload timer the functions of the 16-bit reload timer are as follows : ? choose one of three internal clocks or an external event clock as the count clock. ? choose a software or external launch trigger. ? an interrupt can be sent to the cpu in response to an underflow generated by the 16-bit timer register. interrupts can be used to utilize the timer as an interval timer. ? when an underflow is generated by the 16-bit timer register (tmr) , select one-shot mode, where tmr counter operation is halted, or reload mode, where the 16-bit reload register value is reloaded, and tmr count operation continues. ? supports extended intelligent i/o service (ei 2 os) . ? the mb90495g series features two on-chip 16-bit reload timer channels. ? 16 - bit reload timer operation mode ? internal clock mode ? set the count clock selection bits of the timer control status register (tmcsr : csl1, csl0) to 00 b , 01 b or 10 b to set the 16-bit reload timer to internal clock mode. ? in internal clock mode, the timer counts down in synchronization with the internal clock. ? set the count clock selection bits of the timer control status register (tmcsr : csl1, csl0) to select one of three count clock intervals. ? select software-triggered or externally triggered (edge detection) launch. count clock launch trigger operation in case of underflow internal clock mode software trigger external trigger one-shot mode reload mode event count mode software trigger one-shot mode reload mode
mb90495g series 43 ? 16-bit reload timer block diagram tmrlr tmr clk tin uf en tot clk 3 3 2 ???? csl1 csl0 mod2 mod1 mod0 oute outl reld uf inte cnte trg count clock generation circuit machine clock f pin pin 16-bit timer register prescaler clear 16-bit reload register gate input internal clock external clock internal data bus valid clock determination circuit clock selector select signal reload signal wait signal output control circuit output signal generation circuit reload control circuit output to on-chip peripheral functions operation control circuit timer control status register (tmcsr) select function i/o control circuit output interrupt request
mb90495g series 44 6. watch timer the watch timer is a 15-bit free-run counter that counts up in synchronization with the subclock. ? eight different intervals can be selected, and interrupt requests generated for each interval time. ? supplies a timer for subclock oscillation stabilization standby, and an operational clock for the watchdog timer. ? the subclock is always the count clock, regardless of the clock selection register (ckscr) setting. ? interval timer feature ? when the interval time set by the interval time selection bits (wtc : wtc2 to wtc0) is reached, the clock timer generates an overflow in the bits corresponding to the interval time of the watch timer counter, and sets the overflow flag bit (wtc : wtof = 1) . ? interrupts arising from overflows are enabled (wtc : wtie = 1) , an interrupt request is generated when the overflow flag bit is set (wtc : wtof = 1) . ? select from one of the following 8 watch timer intervals : clock timer interval times sclk : subclock frequency figures in parentheses ( ) are a sample calculation with the subclock running at 8.192 khz. subclock frequency interval time sclk (122 m s) 2 8 /sclk (31.25 ms) 2 9 /sclk (62.5 ms) 2 10 /sclk (125 ms) 2 11 /sclk (250 ms) 2 12 /sclk (500 ms) 2 13 /sclk (1.0 s) 2 14 /sclk (2.0 s) 2 15 /sclk (4.0 s)
mb90495g series 45 ? watch timer block diagram wdcs sce wtie wtof wtr wtc2 wtc1 wtc0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 2 10 2 11 2 12 2 13 2 15 2 14 of of of of of of of of sclk watch timer counter watch timer control register (wtc) power-on reset go to hardware standby go to stop mode watch timer interrupt counter clear circuit interval timer selector to watchdog timer to subclock oscillation stabilization standby time of : overflow sclk : subclock notes: the actual interrupt request number generated by the watch timer is as follows : interrupt request number : #28 (1c h ) watch timer counter: 15-bit up counter using the subclock (sclk) as its count clock. counter clear circuit: this circuit clears the watch timer counter.
mb90495g series 46 7. 8/16-bit ppg the 8/16-bit ppg timer is a 2-channel reload timer module (ppg0, ppg1) capable of arbitrary synchronization and pulse output of duty ratio. combining the 2 channel module can yield the following behavior : ? 8-bit ppg output, 2-channel independent operation mode ? 16-bit ppg output operation mode ? 8 + 8-bit ppg output operation mode the mb90495g series features two on-chip, 8/16-bit ppg timers. this section describes the functions of ppg0/ 1. ppg2/3 has the same functions as ppg0/1. ? 8/16-bit ppg timer functions the 8/16-bit ppg timer is made up of four 8-bit reload registers (prlh0/prll0, prlh1/prll1) , and two ppg down counters (pnt0, pcnt1) . ? since you can set each output pulse to h or l width independently, the interval and duty ratio of each pulse can be set to an arbitrary value. ? select one of 6 internal clocks as the count clock. ? interrupt requests can be generated for each interval time, allowing the timer to be used as an interval timer. ? the use of an external circuit allows the timer to be used as a d/a converter.
mb90495g series 47 ? block diagram of 8/16-bit ppg timer 0 ppg0 clk r sq pen0 pe0 pie0 puf0 ?? ? pcs2 pcs0 pcm2 pcm1 pcm0 ?? pcs1 3 2 ppg0 reload register prlh0 ("h" level side) ppg0 temporary buffer 0 (prlbh0) reload register l/h selector initial count value ppg0 down counter (pcnt0) prll0 ("l" level side) select signal reload underflow time-base timer output (512/hclk) clear invert ppg0 output latch count clock selector select signal ppg0/1 count clock selection register (ppg01) ppg0 operation mode control register (ppgc0) pulse selector "h" level side data bus "l" level side data bus ppg output control circuit re- served output interrupt request* operation mode control signal ppg0 underflow ppg1 underflow (to ppg1) pin peripheral clock (16/ f ) peripheral clock (8/ f ) peripheral clock (4/ f ) peripheral clock (2/ f ) peripheral clock (1/ f ) ? : undefined reserved : reserved bit hclk : oscillation clock frequency f : machine clock frequency * : interrupt output from 8/16-bit ppg timer 0 is merged with interrupt request output from ppg timer 1 into a single interrupt via an or circuit.
mb90495g series 48 ? block diagram of 8/16-bit ppg timer1 ppg1 clk md0 r sq pen1 pe10 pie1 puf1 md1 md0 ? pcs2 pcs0 pcm2 pcm1 pcm0 ?? pcs1 3 2 ppg1 reload register operation mode control signal ppg1 underflow (to ppg0) ppg0 underflow (from ppg0) prlh1 ("h" side) ppg1 temporary buffer (prlbh1) reload selector l/h selector initial count value ppg1 down counter (pcnt1) prll1 ("l" side) reload underflow time-base timer output (512/hclk) peripheral clock (1/ f ) peripheral clock (2/ f ) peripheral clock (4/ f ) peripheral clock (8/ f ) peripheral clock (16/ f ) select signal clear invert ppg1 output latch ppg output control circuit select signal counter clock selector ppg0/1 count clock selection register (ppg01) "h" level side data bus "l" level side data bus ppg1 operation mode control register (ppgc1) re- served output interrupt request* pin ? : undefined reserved : reserved bit hclk : oscillation clock frequency f : machine clock frequency * : interrupt output from 8/16-bit ppg timer 1 is merged with interrupt request output from ppg timer 0 into a single interrupt via an or circuit.
mb90495g series 49 8. delayed interrupt generation module the delayed interrupt generation module generates interrupts for switching tasks. this module can be used to generate hardware interrupts from the software. ? overview of the delayed interrupt generation module use the delayed interrupt generation module to generate or cancel hardware interrupts from the software. overview of the delayed interrupt generation module ? delayed interrupt/generation module block diagram ? interrupt number below is the interrupt number used by the delayed interrupt generation module. interrupt number : #42 (2a h ) functions and control interrupt condition when the r0 bit of the delayed interrupt request generation/cancel register is set to 1 (dirr : r0 = 1) : generate interrupt request when the r0 bit of the delayed interrupt request generation/cancel register is set to 0 (dirr : r0 = 0) : cancel interrupt request interrupt number #42 (2a h ) interrupt control there is no enable setting from the register interrupt flag stored in bit dirr : r0 ei 2 os does not support extended intelligent i/o service ??????? r0 s r internal data bus delayed interrupt request generation/cancel register (dirr) interrupt request latch interrupt request signal ? : undefined interrupt request latch:this latch stores the delayed interrupt request generation/cancel register setting (generates/cancels delayed interrupt requests) . delayed interrupt request generation/cancel register (dirr) : generates or cancels delayed interrupt requests.
mb90495g series 50 9. dtp/external interrupts the dtp/external interrupt transmits interrupt requests or data transfer requests generated by peripheral devices to the cpu, generates external interrupt request, and starts the extended intelligent i/o service (ei 2 os) . ? dtp/external interrupt functions outputs interrupt requests from external peripheral devices to the cpu using the same procedure as for periph- eral functions, and generates external interrupts, or starts the extended intelligent i/o service (ei 2 os) . if the interrupt control register is configured to prohibit the extended intelligent i/o service (ei 2 os) (icr : ise = 0) , then the external interrupt feature becomes valid, and the process branches into interrupt processing. if the ei 2 os is enabled (icr : ise = 1) , then the dtp function becomes valid, and the ei 2 os automatically transmits data, and after transmitting data a specified number of times, branches into interrupt processing. overview of dtp/external interrupts external interrupt dtp functions input pins 8 (int0 to int7) interrupt condition each pin sets individually in the detection level configuration register (elvr) h / l level/rising edge/falling edge input h / l level input interrupt numbers #15 (0f h ) , #20 (14 h ) , #24 (18 h ) , #27 (1b h ) interrupt control the dtp/external interrupt enable register (enir) enables or prohibits interrupt request output interrupt flag interrupt conditions stored by dtp/external interrupt condition register (eirr) process selection set ei 2 os to prohibited (icr : ise = 0) set ei 2 os to enabled (icr : ise = 1) processing branch to external interrupt process after the ei 2 os conducts automated data forwarding the specified number of times, branches to interrupt processing.
mb90495g series 51 ? dtp/external interrupt block diagram int7 int6 int5 int4 lb7 la7 lb6 la6 lb5 la5 lb4 la4 er7 er6 er5 er4 er3 er2 int3 int2 int1 int0 lb3 la3 lb2 la2 lb1 la1 lb0 la0 er1 er0 en7 en6 en5 en4 en3 en2 en1 en0 internal data bus detection level configuration register (elvr) pin pin pin pin dtp/external interrupt input detection circuit interrupt request signal level/ edge selector level/ edge selector level/ edge selector level/ edge selector level/ edge selector level/ edge selector level/ edge selector level/ edge selector pin pin pin pin dtp/external interrupt condition register (eirr) interrupt request signal dtp/external interrupt enable register (enir)
mb90495g series 52 10. 8/10-bit a/d converter the 8/10-bit a/d converter converts analog voltage to 8 or 10-bit digital values, by means of rc successive approximation conversion. ? the input signal can be selected from an 8-channel analog input pin set. ? select a software trigger, internal timer output, or external trigger as the start trigger. ? functions of the 8/10 a/d converter converts analog voltage (input voltage) input to the analog input pins to 8-bit or 10-bit digital values. (a/d conversion) the 8/10-bit a/d converter has the following features : ? single-channel a/d conversion time is a minimum of 6.12 m s, including sampling time.* ? single-channel sampling time is a minimum of 2.0 m s.* ? rc-type successive approximation with sampling and hold circuits is used for conversion. ? select 8 or 10-bit resolution. ? analog input pins can use up to 8 channels. ? a/d conversion results are stored in the a/d data register, allowing them to be used to generate interrupts. ? interrupt requests launch the ei 2 os. use the ei 2 os to prevent dropped data even with continuous a/d con- version. ? select software, internal timer output, or external trigger (falling edge) as the start trigger. * : with machine clock operating at 16 mhz ? conversion modes of the 8 / 10 - bit a / d converter conversion mode description single conversion mode conducts a/d conversion for each channel in turn, from the start channel to the end channel. when a/d conversion of the end channel is completed, the a/d conversion function halts. continuous conversion mode conducts a/d conversion for each channel in turn, from the start channel to the end channel. when a/d conversion of the end channel is completed, the function returns to the start channel and continues a/d conversion. stop conversion mode suspends each channel and conducts a/d conversion, one at a time. when a/d conversion of the end channel is completed, the function returns to the start channel and repeats the a/d conversion and channel stop.
mb90495g series 53 ? 8/10-bit a/d converter block diagram busy int inte paus sts1 sts0 stat md1 md0 ans2 ans1 ans0 ane2 ane1 ane0 an7 an6 adtg to an5 an4 an3 an2 an1 an0 avr av cc av ss 2 6 2 2 2 f s10 st1 st0 ct1 ct0 ? d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 a/d control status register (adcs) a/d data register (adcr) launch selector analog channel selector output interrupt request re- served sample and hold circuit decoder comparator control circuit d/a converter internal data bus to : internal timer output ? : undefined reserved : make sure this is always set to 01 f : machine clock
mb90495g series 54 11. uart0/1 the uart is a general-purpose serial data communications interface for synchronous or asynchronous com- munication with external devices. ? the uart has a clock-synchronous/clock-asynchronous two-way communications feature . ? also supplies a master/slave communications feature (multi-processor mode) . (it can be used only master side.) ? interrupts can be generated upon send complete, receive complete, or reception error detection. ? supports extended intelligent i/o service (ei 2 os) . ? uart0/1 functions note : during clock-synchronous forwarding, just the data is forwarded, with no stop or start bit appended. functions data buffer full-duplex double buffer transfer mode ? clock-synchronous (no start, stop, or parity bit) ? clock-asynchronous (start-stop synchronization) baud rate ? select from 8 dedicated baud rate generators ? external clock input possible ? clock supplied from internal timer (16-bit reload timer) available data length ? 7-bit (asynchronous normal mode only) ?8-bit signal method non return to zero (nrz) reception error detection ? framing error ? overrun error ? parity error (not available in operation mode 1 (multi processor mode) ) interrupt requests ? receive interrupt (reception complete, reception error detected) ? send interrupt (send complete) ? both send and receive support extended intelligent i/o service (ei 2 os) master/slave communications function (in multiprocessor mode) 1-to-n (master to slave) communication available (can only be used as master)
mb90495g series 55 ? uart0 block diagram sck0 sin0 sot0 md1 md0 cs2 cs1 cs0 soe scke md div3 div2 div0 div1 pen p sbl cl a / d rec txe rxe pe ore fre rdrf tdre tie rie neg dedicated baud rate generator 16-bit reload timer0 pin pin serial edge selection register clock selector reception status determination circuit reception clock communi- cations prescaler control register control bus reception control circuit start bit detection circuit reception bit counter reception parity counter reception shift register serial input data register0 internal data bus serial mode register0 send clock re- ception end send control circuit send start circuit send bit counter send parity counter send shift register serial output data register0 serial control register0 reception interrupt request output send interrupt request output pin send start ei 2 os receive error generation signal (to cpu) serial status register0
mb90495g series 56 ? uart1 block diagram sck1 sin1 sot1 dedicated baud rate generator 16-bit reload timer1 pin pin clock selector reception status determination circuit reception clock communi- cations prescaler control register control bus reception control circuit start bit detection circuit reception bit counter reception parity counter reception shift register serial input data register1 internal data bus serial mode register1 send clock re- ception end send control circuit send start circuit send bit counter send parity counter send shift register serial output data register1 serial control register1 reception interrupt request output send interrupt request output pin send start ei 2 os receive error generation signal (to cpu) serial status register1 pe ore fre rdrf tdre tie rie pen p sbl cl a / d rec txe rxe md div2 div0 div1 md1 md0 cs2 cs1 cs0 soe scke bds rst
mb90495g series 57 12. can controller can (controller area network) is a serial communications protocol conforming to can version 2.0 a and b. sending and receiving is available in standard and extended frame format. ? can controller features ? the can controller format conforms to can versions 2.0 a and b. ? sending and receiving is available in standard and extended frame format. ? supports automated data frame formatting through remote frame reception. ? baud rate : 10 kbps to 1 mbps. when using at 1 mbps, the machine clock must be operated at 8 mhz or more. data transmission baud rates ? supplies 8 send/receive message buffers. ? sending and receiving available in standard frame format (id 11-bit) , and extended frame format (id 29-bit) . ? message data can be set to 0 to 8 bytes. ? possible to configure a multi-level message buffer. ? the can controller has two built-in acceptance masks, each of which can be set to a different mask for reception message ids. ? the two acceptance masks can receive in standard or extended frame format. ? configure four types of partial masks with full-bit compare, full-bit mask, and acceptance mask register 0/1. machine clock baud rate (max) 16 mhz 1 mbps 12 mhz 1 mbps 8 mhz 1 mbps 4 mhz 500 kbps 2 mhz 250 kbps
mb90495g series 58 ? can controller block diagram btr psc ts1 ts2 rsj toe ns1,0 nt nie halt rs ts csr rtec bvalr treqr tcanr trtrr rfwtr tcr tier rcr rier rrtrr rovrr amsr amr0 amr1 ider leir idr0 to idr7 dlcr0 to dlcr7 dtr0 to dtr7 ram 0 1 rx tx ei 2 os -16lx bus cpu operation clock prescaler (1:1 to 1:64) node status transition interrupt generation circuit clear send buffer send buffer determination circuit send buffer set/clear send buffer send complete interrupt generation circuit set reception buffer reception complete interrupt generation circuit reception buffer set/clear send buffer set reception buffer select id acceptance filter ram address generation circuit bit timing generation circuit node status transition interrupt signal error control circuit send buffer send complete interrupt signal reception complete interrupt signal reception buffer determination circuit reception buffer reception buffer/ send buffer/ receive dlc/send dlc/ select id operation clock (tq) sink segment timer segment 1 timer segment 2 send/receive sequence data counter acceptance filter control circuit send dlc re- ception dlc id selection bit error/ staff error/ crc error/ frame error/ ack error send shift register receive dlc reception shift register arbitration lost bit error ack error frame error crc generation circuit crc error crc generation circuit/error check bus status determina- tion circuit error frame generation circuit overload frame generation circuit arbitration lost staffing ack generation circuit staff error destaffing/ staffing error check arbitration check bit error check acknowledgement error check form error check idle/ interrupt/ suspend/ send/ receive/ error/ overload output driver pin input latch pin send dlc
mb90495g series 59 13. rom correction function in the case that the address of the instruction after the one that a program is currently processing matches the address configured in the detection address configuration register, the program forces the next instruction to be processed into an int9 instruction, and branches to the interrupt process program. since processing can be conducted using int9 interrupts, programs can be repaired using batch processing. ? overview of the rom correction function ? the address of the instruction after the one that a program is currently processing is always stored in an address latch via the internal data bus. rom correction constantly compares the address stored in the address latch with the one configured in the detection address configuration register. if the two compared addresses match, the cpu forcibly changes this instruction into an int9 instruction, and executes an interrupt processing program. ? there are two detection address configuration registers : padr0 and padr1. each register provides an interrupt enable bit. this allows you to individually configure each register to enable/prohibit the generation of interrupts when the address stored in the address latch matches the one configured in the detection address configuration register. ? rom correction block diagram ? address latch stores value of address output to internal data bus. ? address detection control register (pacsr) set this register to enable/prohibit interrupt output when an address match is detected. ? detection address configuration register (padr0, padr1) configure an address with which to compare the address latch value. ad1e ad0e padr1 (24 bit) padr0 (24 bit) pacsr internal data bus address latch detection address configuration register 0 detection address configuration register 1 re- served re- served re- served re- served re- served re- served address detection control register (pacsr) comparator int9 instruction (int9 interrupt generation) reserved : make sure this is always set to 01
mb90495g series 60 14. rom mirror function selection module the rom mirror function selection module configures rom-internal data arrayed inside bank ff to be readable by accessing bank 00. ? rom mirror function selection module block diagram ? accessing bank ff through rom mirror function rom internal data bus address data bank ff rom mirror function selection register (romm) address area bank 00 mi reserved reserved reserved reserved reserved reserved reserved 004000 h 00ffff h feffff h ff0000 h ff4000 h ffffff h mb90f497g mb90497g bank 00 bank ff (area corresponding to rom mirror) rom mirror area fc0000 h fe0000 h mb90f498g mb90v495g
mb90495g series 61 15. 512-k/1-m bit flash memory ? overview there are three methods available for writing/deleting data to/from flash memory : 1. parallel writer 2. serial dedicated writer 3. program runtime write/delete ? overview of 512-k/1-m bit flash memory 512-kbit flash memory is arrayed in bank ff h on the cpu memory map, 1-mbit flash memory is arrayed in bank fe h to ff h on the cpu memory map. the flash memory interface circuit provides read and program access from the cpu. since instructions from the cpu are carried out via the flash memory interface circuit, flash memory can be overwritten at the implementation level. this allows you to efficiently improve programs and data. ? features of 512-k/1-m bit flash memory ? 512-kbit flash memory : 64 kwords 8-bit/32 kwords 16-bit (16 kbyte + 8 kbyte + 8 kbyte + 32 kbyte) sector architecture ? 1-mbit flash memory : 128 kwords 8-bit/64 kwords 16-bit (16 kbyte + 8 kbyte + 8 kbyte + 32 kbyte + 64 kbyte) sector architecture ? auto program algorithm (embedded algorithm tm : same as mbm29lv200) ? on-chip delete suspend/delete resume functions ? data polling, write/delete completion detection through toggle bit ? write/delete completion detection from cpu overwrite ? sector-specific deletion available (sectors can be combined as desired) ? write/delete iterations (minimum) : 10,000 embedded algorithm tm is a trademark of advanced micro device. notes : there is no function to read the manufacture or device code. these codes also cannot be accessed through commands. ? flash memory write/delete ? it is not possible to simultaneously write to and read from flash memory. ? when writing to or deleting from flash memory, first copy the program residing in flash memory into ram, then execute the program copied into ram. this will allow you to write to flash memory.
mb90495g series 62 ? list of flash memory registers and reset values ? sector architecture of 512-k/1-m bit flash memory ? sector architecture 512-kbit flash memory : when accessing from the cpu, sa0 to sa3 are arrayed in the bank ff register. 1-mbit flash memory : when accessing from the cpu, sa0 is arrayed in the bank fe register, sa1 to sa4 are arrayed in the bank ff register. sector architecture of 512-k/1-m bit flash memory 7 bit 65 4321 0 0 00x0000 : undefined flash memory control status register (fmcs) ff0000 h ff7fff h ff8000 h ff9fff h ffa000 h ffbfff h ffc000 h ffffff h 70000 h 77fff h 78000 h 79fff h 7a000 h 7bfff h 7c000 h 7ffff h sa0 (32 kbytes) sa1 (8 kbytes) sa2 (8 kbytes) sa3 (16 kbytes) 512-kbit flash memory cpu addresses writer address* * : if a parallel write is writing data to flash memory, the write address corresponds to the cpu address. if a general-purpose writer is used to write/delete, this address is written to/over. fe0000 h feffff h ff0000 h ff7fff h ff8000 h ff9fff h 60000 h 6ffff h 70000 h 77fff h 78000 h 79fff h ffa000 h ffbfff h 7a000 h 7bfff h sa0 (64 kbytes) sa1 (32 kbytes) sa2 (8 kbytes) sa3 (8 kbytes) 1-mbit flash memory cpu addresses writer address* ffc000 h ffffff h 7c000 h 7ffff h sa4 (16 kbytes)
mb90495g series 63 n electrical characteristics 1. absolute maximum ratings (v ss = av ss = 0 v) *1 : av cc and avr shall never exceed v cc . also, avr shall never exceed av cc . *2 : v i and v o shall never exceed v cc + 0.3 v. however, if the maximum current to/from an input is limited by some means with external components, the i clamp rating supersedes the v i rating. *3 : the rating for the maximum output current is the peak value of one of the corresponding pins. *4 : the standard for computing average output current is the average current output from one of the corresponding pins over a period of 100 ms (the average value is taken by multiplying operating current by operational rate) . *5 : the standard for computing average total output current is the average current output from all of the corre- sponding pins over a period of 100 ms (the average value is taken by multiplying operating current by operational rate) . *6 : applicable to pins: p00 to p07, p10 to p17, p20 to p27, p30 to p37, p40 to p44, p50 to p57, p60 to p63 use within recommended operating conditions. use at dc voltage (current) the + b signal should always be applied a limiting resistance placed between the + b signal and the microcontroller. the value of the limiting resistance should be set so that when the + b signal is applied the input current to the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods. note that when the microcontroller drive current is low, such as in the power saving modes, the + b input potential may pass through the protective diode and increase the potential at the v cc pin, and this may affect other devices. (continued) parameter symbol rating unit remarks min max power supply voltage v cc v ss - 0.3 v ss + 6.0 v av cc v ss - 0.3 v ss + 6.0 v v cc = av cc * 1 avr v ss - 0.3 v ss + 6.0 v av cc 3 avr * 1 input voltage v i v ss - 0.3 v ss + 6.0 v * 2 output voltage v o v ss - 0.3 v ss + 6.0 v * 2 maximum clamp current i clamp - 2.0 + 2.0 ma * 6 total maximum clamp current s | i clamp | ? 20 ma * 6 l level maximum output current i ol ? 15 ma * 3 l level average output current i olav ? 4ma * 4 l level maximum total output current s i ol ? 100 ma l level average total output current s i olav ? 50 ma * 5 h level maximum output current i oh ?- 15 ma * 3 h level average output current i ohav ?- 4ma * 4 h level maximum total output current s i oh ?- 100 ma h level average total output current s i ohav ?- 50 ma * 5 power consumption p d ? 315 mw operating temperature t a - 40 + 105 c - 40 + 125 c* 7 storage temperature t stg - 55 + 150 c
mb90495g series 64 (continued) note that if a + b signal is input when the microcontroller power supply is off (not fixed at 0 v) , the power supply is provided from the pins, so that incomplete operation may result. note that if the + b input is applied during power-on, the power supply is provided from the pins and the resulting supply voltage may not be sufficient to operate the power-on reset. care must be taken not to leave the + b input pin open. note that analog system input/output pins other than the a/d input pins (lcd drive pins, comparator input pins, etc.) cannot accept + b signal input. sample recommended circuits: *7 : if used exceeding t a = + 105 c, be sure to contact us for reliability limitations. warning: semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. p-ch n-ch v cc r + b input (0 v to 16 v) limiting resistance protective diode
mb90495g series 65 2. recommended operating conditions (v ss = av ss = 0.0 v) *1 : use a ceramic capacitor, or one with approximately the same frequency characteristics. the bypass capacitor of the v cc pin should have a greater capacity than c s . see the figure below for details about connecting a smooth capacitor to the c s . *2 : if used exceeding t a = + 105 c, be sure to contact us for reliability limitations. warning: the recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. all of the devices electrical characteristics are warranted when the device is operated within these ranges. always use semiconductor devices within their recommended operating condition ranges. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu representatives beforehand. parameter symbol value unit remarks min typ max power supply voltage v cc , av cc 4.5 5.0 5.5 v during normal operation, t a = - 40 c to + 105 c 4.75 5.0 5.25 v during normal operation, + 105 c < t a + 125 c 3.0 ? 5.5 v maintaining stop operation state smoothing capacitor c s 0.022 0.1 1.0 m f*1 operating temperature t a - 40 ?+ 105 c - 40 ?+ 125 c*2 c c s ? c pin connection diagram
mb90495g series 66 3. dc characteristics (v cc = 5.0 v 5 % , v ss = av ss = 0.0 v, t a = - 40 c to + 125 c) (v cc = 5.0 v 10 % , v ss = av ss = 0.0 v, t a = - 40 c to + 105 c) (continued) parameter sym- bol pin name condition value unit remarks min typ max h level input voltage v ihs cmos hysteresis input pin ? 0.8 v cc ? v cc + 0.3 v v ihm md input pin ? v cc - 0.3 ? v cc + 0.3 v l level input voltage v ils cmos hysteresis input pin ? v ss - 0.3 ? 0.2 v cc v v ilm md input pin ? v ss - 0.3 ? v ss + 0.3 v h level output voltage v oh all output pins v cc = 4.5 v, i oh = - 4.0 ma v cc - 0.5 ?? vt a = - 40 c to + 105 c v cc = 4.75 v v cc - 0.5 ?? v + 105 c < t a + 125 c l level output voltage v ol all output pins v cc = 4.5 v, i ol = 4.0 ma ?? 0.4 v t a = - 40 c to + 105 c v cc = 4.75 v ?? 0.4 v + 105 c < t a + 125 c input leakage current i il all output pins v cc = 5.5 v, v ss < v i < v cc - 5 ? 5 m at a = - 40 c to + 105 c v cc = 5.25 v, v ss < v i < v cc - 5 ? 5 m a + 105 c < t a + 125 c power supply current* i cc v cc v cc = 5.0 v internal 16-mhz operation, normal mode ? 30 40 ma mb90497g mb90f497g mb90f498g v cc = 5.0 v internal 16-mhz operation, flash memory write mode ? 45 50 ma mb90f497g mb90f498g v cc = 5.0 v internal 16-mhz operation, flash memory delete mode ? 45 50 ma mb90f497g mb90f498g i ccs v cc = 5.0 v internal 16-mhz operation, sleep mode ? 11 18 ma mb90497g mb90f497g mb90f498g
mb90495g series 67 (continued) (v cc = 5.0 v 5 % , v ss = av ss = 0.0 v, t a = - 40 c to + 125 c) (v cc = 5.0 v 10 % , v ss = av ss = 0.0 v, t a = - 40 c to + 105 c) * : this is when using the external clock as the power supply current test condition. parameter sym- bol pin name condition value unit remarks min typ max power supply current* i cts v cc v cc = 5.0 v internal 2-mhz operation, timer mode ? 0.6 1.2 ma mb90497g mb90f497g mb90f498g i ccl v cc = 5.0 v internal 8-khz operation, subclock operation mode t a = + 25 c ? 30 50 m a mb90497g ? 300 500 m a mb90f497g mb90f498g i ccls v cc = 5.0 v internal 8-khz operation, subclock sleep mode t a = + 25 c ? 10 30 m a mb90497g mb90f497g mb90f498g i cct v cc = 5.0 v internal 8-khz operation, clock mode t a = + 25 c ? 825 m a mb90497g mb90f497g mb90f498g power supply current* i cch v cc v cc = 5.0 v stop mode, t a = + 25 c ? 520 m a mb90497g mb90f497g mb90f498g input capacity c in other than av cc , av ss , avr, c, v cc , or v ss ?? 515pf pull up resistor r up rst ? 25 50 100 k w pull down resistor r down md2 ? 25 50 100 k w
mb90495g series 68 4. ac characteristics (1) clock timing (v cc = 5.0 v 5 % , v ss = av ss = 0.0 v, t a = - 40 c to + 125 c) (v cc = 5.0 v 10 % , v ss = av ss = 0.0 v, t a = - 40 c to + 105 c) parameter symbol pin name value unit remarks min typ max clock frequency f c x0, x1 3 ? 16 mhz f cl x0a, x1a ? 32.768 ? khz clock cycle time t hcyl x0, x1 62.5 ? 333 ns t lcyl x0a, x1a ? 30.5 ?m s input clock pulse width p wh , p wl x0 10 ?? ns duty ratio should be around 30 % to 70 % p wlh , p wll x0a ? 15.2 ?m s input clock rising/falling time t cr , t cf x0 ?? 5 ns when external clock used internal operation clock frequency f cp ? 1.5 ? 16 mhz when oscillation circuit used f lcp ?? 8.192 ? khz when subclock used internal operation clock cycle time t cp ? 62.5 ? 666 ns when using oscillation circuit t lcp ?? 122.1 ?m s when subclock used x0 t hcyl t cf t cr 0.8 v cc 0.2 v cc p wh p wl x0a t lcyl t cf t cr 0.8 v cc 0.2 v cc p wlh p wll ? x0/x1 clock timing
mb90495g series 69 ac characteristics are specified by the following reference voltage values. 5.5 4.5 3.0 3.3 81.5 3 1 2 1 6 pll guaranteed operation range mb90f497g/mb90f498g/mb90497g gua r anteed ope r ation r ange (t a = - 40 c to + 105 c) power supply voltage v cc (v) internal clock f cp (mhz) 5.25 4.75 mb90f497g/mb90f498g/mb90497g guaranteed operation range ( = + 105 c < t a + 125 c) 16 12 8 9 4 34 8 16 1/2 (no multiplication) 4 3 2 1 internal clock f cp (mhz) external clock f c (mhz) relationship between external clock frequency and internal operation clock frequency relationship between internal operating clock frequency and power supply voltage ? pll guaranteed operation range 0.8 v cc 0.2 v cc 2.4 v 0.8 v ? input signal waveform hysteresis input pin ? output signal waveform output pin
mb90495g series 70 (2) clock output timing (v cc = 5.0 v 5 % , v ss = av ss = 0.0 v, t a = - 40 c to + 125 c) (v cc = 5.0 v 10 % , v ss = av ss = 0.0 v, t a = - 40 c to + 105 c) (3) reset input timing * : oscillator oscillation time is the time to reach 90 % amplitude. for a crystal oscillator, this is a few to several dozen ms; for a far/ceramic oscillator, this is several hundred m s to a few ms, and for an external clock this is 0 ms. parameter symbol pin name condition value unit remarks min max cycle time t cyc clk ? 62.5 ? ns clk - ? clk t chcl 20 ? ns parameter symbol pin name condition value unit remarks min max reset input time t rstl rst ? 16 t cp ? ns normal mode oscillator oscillation time* + 16 t cp ? ms stop mode, watch mode, subclock mode, subsleep mode clk t cyc 2.4 v 2.4 v 0.8 v t chcl t rstl 0.2 v cc 0.2 v cc 16 t cp rst x0 90% of amplitude instruction execution oscillation stabilize standby time oscillator oscillation time internal operation clock internal reset ? stop mode, watch mode, subclock mode, subsleep mode
mb90495g series 71 (4) power-on reset (v cc = 5.0 v 5 % , v ss = av ss = 0.0 v, t a = - 40 c to + 125 c) (v cc = 5.0 v 10 % , v ss = av ss = 0.0 v, t a = - 40 c to + 105 c) parameter symbol pin name condition value unit remarks min max power supply rising time t r v cc ? 0.05 30 ms power supply cutoff time t off v cc 1 ? ms due to repeated operations v cc v cc v ss 3 v t r t off 2.7 v 0.2 v 0.2 v 0.2 v ram data hold period it is recommended that you keep the rising speed to no more than 50 mv/ms. sudden changes in the power supply voltage may cause a power-on reset. to change the power supply voltage while the device is in operation, it is recommended that you raise the voltage at a steady rate, in order to suppress fluctuations (see figure below). in this case, perform this operation when the pll clock is not being used. if, however, the voltage falling speed is no more than 1 v/s, it is permissible to perform this operation while using the pll clock.
mb90495g series 72 (5) bus read timing (v cc = 5.0 v 10 % , v ss = 0.0 v, t a = - 40 c to + 105 c) parameter symbol pin name value unit remarks min max ale pulse width t lhll ale t cp /2 - 20 ? ns valid address ? ale time t avll ale, a23 to a16, ad15 to ad00 t cp /2 - 20 ? ns ale ? address valid time t llax ale, ad15 to ad00 t cp /2 - 15 ? ns valid address ? rd time t avrl a23 to a16, ad15 to ad00, rd t cp - 15 ? ns valid address ? valid data input t avdv a23 to a16, ad15 to ad00 ? 5 t cp /2 - 60 ns rd pulse width t rlrh rd 3 t cp /2 - 20 ? ns rd ? valid data input t rldv rd , ad15 to ad00 ? 3 t cp /2 - 60 ns rd - ? data hold time t rhdx rd , ad15 to ad00 0 ? ns rd ? ale - time t rhlh rd , ale t cp /2 - 15 ? ns rd - ? address valid time t rhax rd , a23 to a16 t cp /2 - 10 ? ns valid address ? clk - time t avch a23 to a16, ad15 to ad00, clk t cp /2 - 20 ? ns rd ? clk - time t rlch rd , clk t cp /2 - 20 ? ns ale ? rd time t llrl ale, rd t cp /2 - 15 ? ns
mb90495g series 73 0.8 v 0.8 v 2.4 v 2.4 v 2.4 v 2.4 v 0.8 v 2.4 v 0.8 v 2.4 v 0.8 v 2.4 v 0.2 v cc 0.8 v cc clk ale rd a23 to a16 ad15 to ad00 t rhlh t avrl t avll t llax t lhll t rlrh t rhax t rhdx t rlch 2.4 v 2.4 v 0.8 v t avch 0.2 v cc 0.8 v cc t avdv t rldv 2.4 v t llrl address read data ? bus read timing
mb90495g series 74 (6) bus write timing (v cc = 5.0 v 10 % , v ss = 0.0 v, t a = - 40 c to + 105 c) parameter symbol pin name value unit remarks min max valid address ? wr time t avwl a23 to a16, ad15 to ad00, wr t cp - 15 ? ns wr pulse width t wlwh wr 3 t cp /2 - 20 ? ns valid data output ? wr - time t dvwh ad15 to ad00, wr 3 t cp /2 - 20 ? ns wr - ? data hold time t whdx ad15 to ad00, wr 20 ? ns wr - ? address valid time t whax a23 to a16, wr t cp /2 - 10 ? ns wr - ? ale - time t whlh wr , ale t cp /2 - 15 ? ns wr - ? clk - time t wlch wr , clk t cp /2 - 20 ? ns 0.8 v 0.8 v 2.4 v 2.4 v 2.4 v 2.4 v 0.8 v 2.4 v 0.8 v 2.4 v 0.8 v 2.4 v 0.8 v 2.4 v clk ale wr (wrl, wrh) a23 to a16 ad15 to ad00 t whlh t avwl t wlwh t whax t whdx t wlch t dvwh address write data
mb90495g series 75 (7) ready input timing (v cc = 5.0 v 10 % , v ss = 0.0 v, t a = - 40 c to + 105 c) note : use the automatic ready function if the setup time for the falling edge of the rdy signal is not sufficient. (8) hold timing (v cc = 5.0 v 10 % , v ss = 0.0 v, t a = - 40 c to + 105 c) note : it will take at least 1 cycle from the time the hrq pin is loaded until the hak changes. parameter symbol pin name value unit remarks min max rdy setup time t ryhs rdy 45 ? ns rdy hold time t ryhh rdy 0 ? ns parameter symbol pin name value unit remarks min max pin in floating status ? hak time t xhal hak 30 t cp ns hak - ? pin valid time t hahv hak t cp 2 t cp ns t ryhs t ryhh 2.4 v 0.8 v cc 0.2 v cc 0.8 v cc clk ale rd/wr rdy unweighted rdy weighted (1 cycle) ? ready input timing hak t xhal t hahv 2.4 v 0.8 v 2.4 v 2.4 v 0.8 v 0.8 v each pin high-z ? hold timing
mb90495g series 76 (9) uart timing (v cc = 5.0 v 5 % , v ss = 0.0 v, t a = - 40 c to + 125 c) (v cc = 5.0 v 10 % , v ss = 0.0 v, t a = - 40 c to + 105 c) * : see (1) clock timing for details about t cp (internal operating clock cycle time) . notes : ac ratings are for clk synchronous mode. c l is the load capacitor value connected to pins while testing. parameter symbol pin name condition value unit remarks min max serial clock cycle time t scyc sck1 internal shift clock mode output pin : c l = 80 pf + 1 ttl 8 t cp * ? ns sck ? sot delay time t slov sck1, sot1 - 80 80 ns valid sin ? sck - t ivsh sck1, sin1 100 ? ns sck - ? valid sin hold time t shix sck1, sin1 60 ? ns serial clock h pulse width t shsl sck1 eternal shift clock mode outputpin : c l = 80 pf + 1 ttl 4 t cp ? ns serial clock l pulse width t slsh sck1 4 t cp ? ns sck ? sot delay time t slov sck1, sot1 ? 150 ns valid sin ? sck - t ivsh sck1, sin1 60 ? ns sck - ? valid sin hold time t shix sck1, sin1 60 ? ns
mb90495g series 77 ? internal shift clock mode ? external shift clock mode sck sot sin t scyc t slov t ivsh t shix 0.8 v 0.8 v 2.4 v 2.4 v 0.8 v 0.8 v cc 0.2 v cc 0.8 v cc 0.2 v cc sck sot sin t slsh t shsl t slov t ivsh t shix 0.2 v cc 0.2 v cc 0.8 v cc 0.8 v cc 2.4 v 0.8 v 0.8 v cc 0.2 v cc 0.8 v cc 0.2 v cc
mb90495g series 78 (10) timer input timing (v cc = 5.0 v 5 % , v ss = 0.0 v, t a = - 40 c to + 125 c) (v cc = 5.0 v 10 % , v ss = 0.0 v, t a = - 40 c to + 105 c) (11) timer output timing (v cc = 5.0 v 5 % , v ss = 0.0 v, t a = - 40 c to + 125 c) (v cc = 5.0 v 10 % , v ss = 0.0 v, t a = - 40 c to + 105 c) (12) trigger input timing (v cc = 5.0 v 5 % , v ss = 0.0 v, t a = - 40 c to + 125 c) (v cc = 5.0 v 10 % , v ss = 0.0 v, t a = - 40 c to + 105 c) parameter symbol pin name condition value unit remarks min max input pulse width t tiwh tin0, tin1, frck ? 4 t cp ? ns t tiwl in0 to in3, frck parameter symbol pin name condition value unit remarks min max clk - ? t out change time t to tot0, tot1, ppg0 to ppg3 ? 30 ? ns parameter symbol pin name condition value unit remarks min max input pulse width t trgh t trgl int0 to int7, adtg ? 5 t cp ? ns normal mode 1 ?m s stop mode 0.8 v cc 0.8 v cc 0.2 v cc 0.2 v cc t tiwh t tiwl tin0, tin1, in0 to in3, frck ? timer input timing 2.4 v t to 2.4 v 0.8 v clk tot0, tot1, ppg0 to ppg3 ? timer output timing 0.8 v cc 0.8 v cc 0.2 v cc 0.2 v cc t trgh t trgl int0 to int7, adtg ? trigger input timing
mb90495g series 79 5. a/d converter (v cc = av cc = 5.0 v 5 % , v ss = av ss = 0.0 v, 3.0 v avr - av ss , t a = - 40 c to + 125 c) (v cc = av cc = 5.0 v 10 % , v ss = av ss = 0.0 v, 3.0 v avr - av ss , t a = - 40 c to + 105 c) * : current (v cc = av cc = avr = 5.0 v) when a/d converter is not operating and cpu is halted. parameter symbol pin name value unit remarks min typ max resolution ?? ? 10 bit total error ?? ? ? 5.0 lsb nonlinearity error ?? ? ? 2.5 lsb differential linearity error ?? ? ? 1.9 lsb zero transition voltage v ot an0 to an7 av ss - 3.5 lsb av ss + 0.5 lsb av ss + 4.5 lsb v 1 lsb = avr / 1024 full-scale transition voltage v fst an0 to an7 avr - 6.5 lsb avr - 1.5 lsb avr + 1.5 lsb v conversion time ?? 66 t cp ?? ns machine clock of 16 mhz sampling period ?? 32 t cp ?? ns analog port input current i ain an0 to an7 ?? 10 m a analog input voltage v ain an0 to an7 av ss ? avr v reference voltage ? avr av ss + 3.0 ? av cc v power supply current i a av cc ? 27ma i ah av cc ?? 5 m a* reference voltage supply current i r avr ? 0.9 1.3 ma i rh avr ?? 5 m a* inter-channel variation ? an0 to an7 ?? 4lsb
mb90495g series 80 6. a/d converter glossary (continued) resolution : analog changes that are identifiable with the a/d converter linearity error : the deviation of the straight line connecting the zero transition point ( 00 0000 0000 ?? 00 0000 0001 ) with the full-scale transition point ( 11 1111 1110 ?? 11 1111 1111 ) from actual conversion characteristics. differential linearity error : the deviation of input voltage needed to change the output code by 1 lsb from the ideal value. total error : the difference between the actual value and the theoretical value, which includes zero-transition error/full-scale transition error, linearity error, and differential linear- ity error. 3ff 3fe 3fd 004 003 002 001 av ss avr v nt 1.5 lsb 0.5 lsb {1 lsb (n - 1) + 0.5 lsb} actual conversion characteristics (actual measurement) actual conversion characteristics ideal characteristics digital output analog input total error total error of digital output n = v nt - {1 lsb (n - 1) + 0.5 lsb} 1 lsb [lsb] 1 lsb = (ideal value) avr - av ss 1024 [v] v ot (ideal value) = av ss + 0.5 lsb [v] v fst (ideal value) = avr - 1.5 lsb [v] v nt : the voltage to transition digital output from n - 1 to n.
mb90495g series 81 (continued) 7. notes on using a/d converter select the output impedance value for the external circuit of analog input according to the following conditions : external circuit output impedance values of about 5 k w or lower are recommended. if external capacitors are used, a capacitance of several thousand times the internal capacitor value is recom- mended in order to minimize the effect of voltage distribution between the external and internal capacitor. if the output impedance of the external circuit is too high, the sampling time for analog voltages may not be sufficient (sampling period = 2.00 m s @ machine clock of 16 mhz) . ? about error the smaller the absolute value of | avr - av ss |, the greater the relative error. 3ff 3fe 3fd 004 003 002 001 av ss avr av ss avr n + 1 n n - 1 n - 2 v nt v ot (actual measurement) v fst {1 lsb (n - 1) + v ot } actual conversion characteristics (actual measurement) (actual measurement) actual conversion characteristics ideal characteristics actual conversion characteristics actual conversion characteristics ideal characteristics digital output digital output analog input analog input v nt (actual measurement) v (n + 1) t (actual measurement) linearity error differential linearity error linearity error of digital output n = v nt - {1 lsb (n - 1) + v ot } 1 lsb [lsb] differential linearity error of digital output n = v ( n + 1 ) t - v nt 1 lsb - 1 lsb [lsb] v fst - v ot 1022 [v] 1 lsb = v ot : voltage for transition from digital output 000 h to 001 h . v fst : voltage for transition from digital output 3fe h to 3ff h . c comparator analog input r note : the figures given here are the suggested values. mb90f497g, mb90f498g, mb90v495g r 3.2 k w , c 30 pf mb90497g r 2.6 k w , c 28 pf ? model analog input circuit
mb90495g series 82 8. flash memory program/erase characteristics parameter condition value unit remarks min typ max sector erase time t a = + 25 c v cc = 5.0 v ? 115s excludes 00h programming prior erasure chip erare time ? 5 ? s excludes 00h programming prior erasure word (16-bit width) programming time ? 16 3,600 m s excludes system-level overhead erase/program cycle ? 10,000 ?? cycle
mb90495g series 83 n example characteristics ? mb90f497g/f498g (continued) 3.0 4.0 5.0 v cc (v) i cc (ma) 6.0 7.0 45 40 35 30 25 20 15 10 5 0 f = 16 mhz f = 10 mhz f = 8 mhz f = 4 mhz f = 2 mhz 3.0 4.0 5.0 v cc (v) i ccs (ma) 6.0 7.0 16 14 12 10 8 6 4 2 0 f = 16 mhz f = 10 mhz f = 8 mhz f = 4 mhz f = 2 mhz i cc - v cc t a = 25 c, external clock operation f = internal operation frequency i ccs - v cc t a = 25 c, external clock operation f = internal operation frequency
mb90495g series 84 (continued) (continued) 3.0 4.0 5.0 v cc (v) i ccl ( m a) 6.0 7.0 180 f = 8 khz 160 140 120 100 80 60 40 20 0 3.0 4.0 5.0 v cc (v) i ccls ( m a) 6.0 7.0 10 9 8 7 6 5 4 3 2 1 0 f = 8 khz i ccl - v cc t a = 25 c, external clock operation f = internal operation frequency i ccls - v cc t a = 25 c, external clock operation f = internal operation frequency
mb90495g series 85 (continued) 3.0 4.0 5.0 v cc (v) i cct ( m a) 6.0 7.0 7 6 5 4 3 2 1 0 f = 8 khz 0123456 i oh (ma) 7 8 9 10 11 12 v cc - v oh (mv) 1000 900 800 700 600 500 400 300 200 100 0 0123456 i ol (ma) 7 8 9 10 11 12 v ol (v) 1000 900 800 700 600 500 400 300 200 100 0 i cct - v cc t a = 25 c, external clock operation f = internal operation frequency (v cc - v oh ) - i oh t a = 25 c, v cc = 4.5 v v ol - i ol t a = 25 c, v cc = 4.5 v
mb90495g series 86 ? mb90497g (continued) 3.0 4.0 5.0 v cc (v) i cc (ma) 6.0 7.0 45 40 35 30 25 20 15 10 5 0 f = 16 mhz f = 10 mhz f = 8 mhz f = 4 mhz f = 2 mhz 3.0 4.0 5.0 v cc (v) i ccs (ma) 6.0 7.0 16 14 12 10 8 6 4 2 0 f = 16 mhz f = 10 mhz f = 8 mhz f = 4 mhz f = 2 mhz i cc - v cc t a = 25 c, external clock operation f = internal operation frequency i ccs - v cc t a = 25 c, external clock operation f = internal operation frequency
mb90495g series 87 (continued) (continued) 3.0 4.0 5.0 v cc (v) i ccl ( m a) 6.0 7.0 25 20 15 10 5 0 f = 8 khz 3.0 4.0 5.0 v cc (v) i ccls ( m a) 6.0 7.0 10 9 8 7 6 5 4 3 2 1 0 f = 8 khz i ccl - v cc t a = 25 c, external clock operation f = internal operation frequency i ccls - v cc t a = 25 c, external clock operation f = internal operation frequency
mb90495g series 88 (continued) 3.0 4.0 5.0 v cc (v) i cct ( m a) 6.0 7.0 7 6 5 4 3 2 1 0 f = 8 khz 0123456 i oh (ma) 7 8 9 10 11 12 v cc - v oh (mv) 1000 900 800 700 600 500 400 300 200 100 0 0123456 i ol (ma) 7 8 9 10 11 12 v ol (v) 1000 900 800 700 600 500 400 300 200 100 0 i cct - v cc t a = 25 c, external clock operation f = internal operation frequency (v cc - v oh ) - i oh t a = 25 c, v cc = 4.5 v v ol - i ol t a = 25 c, v cc = 4.5 v
mb90495g series 89 n ordering information part number package remarks mb90f497gpf mb90497gpf mb90f498gpf 64-pin plastic qfp (fpt-64p-m06) mb90f497gpfm MB90497GPFM mb90f498gpfm 64-pin plastic lqfp (fpt-64p-m09)
mb90495g series 90 n package dimensions (continued) 64-pin plastic qfp (fpt-64p-m06) note 1) * : these dimensions do not include resin protrusion. note 2) pins width and pins thickness include plating thickness. note 3) pins width do not include tie bar cutting remainder. dimensions in mm (inches) note : the values in parentheses are reference values. c 2003 fujitsu limited f64013s-c-5-5 0.20(.008) m 18.700.40 (.736.016) 14.000.20 (.551.008) 1.00(.039) index 0.10(.004) 119 20 32 52 64 33 51 20.000.20(.787.008) 24.700.40(.972.016) 0.420.08 (.017.003) 0.170.06 (.007.002) 0~8 ? 1.200.20 (.047.008) 3.00 +0.35 C0.20 (mounting height) .118 +.014 C.008 0.25 +0.15 C0.20 .010 +.006 C.008 (stand off) details of "a" part "a" 0.10(.004) * *
mb90495g series 91 (continued) 64-pin plastic lqfp (fpt-64p-m09) note 1) * : these dimensions do not include resin protrusion. note 2) pins width and pins thickness include plating thickness. note 3) pins width do not include tie bar cutting remainder. dimensions in mm (inches) note : the values in parentheses are reference values. c 2003 fujitsu limited f64018s-c-3-5 0.65(.026) 0.10(.004) 116 17 32 49 64 33 48 12.000.10(.472.004)sq 14.000.20(.551.008)sq index 0.320.05 (.013.002) m 0.13(.005) 0.1450.055 (.0057.0022) "a" .059 C.004 +.008 C0.10 +0.20 1.50 0~8 ? 0.25(.010) (mounting height) 0.500.20 (.020.008) 0.600.15 (.024.006) 0.100.10 (.004.004) details of "a" part (stand off) 0.10(.004) *
mb90495g series fujitsu limited all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of fujitsu semiconductor device; fujitsu does not warrant proper operation of the device with respect to use based on such information. when you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of fujitsu or any third party or does fujitsu warrant non-infringement of any third-partys intellectual property right or other right by using such information. fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. the products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). please note that fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. any semiconductor devices have an inherent chance of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade law of japan, the prior authorization by japanese government will be required for export of those products from japan. f0306 ? fujitsu limited printed in japan

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